兼容Cortex-M3指令集嵌入式微处理器设计

发布时间：2018-04-22 13:38

本文选题：嵌入式 + 微处理器　；参考：《南京理工大学》2013年硕士论文

【摘要】：进入21世纪,SoC (System on Chip,片上系统)得到了快速发展,作为SoC最核心的微处理器在各个应用领域扮演了越来越重要的角色。嵌入式微处理器在工业控制、个人消费电子、通信、军工领域有着广泛的应用,其中大部分的SoC芯片采用ARM架构,ARM公司的ARM系列架构的嵌入式微处理器在嵌入式市场占领了大部分市场份额。本文研究了ARM公司Cortex-M系列的Cortex-M3处理器,设计了一款与Cortex-M3指令集完全兼容的嵌入式微处理器,并具有主频高、功耗低的特点。首先,基于Cortex-M3处理器三级流水线,将3级流水线Execution阶段分成Execution、Memory Access、Write Back三个阶段来降低Execution的关键延时,将其扩展为5级流水线,来达到提高主频的目的,提高微处理器性能。其次,采用在处理器软核中加入门控时钟技术来降低处理器的功耗。最后,通过采用哈佛总线结构和双回写机制改善了数据吞吐率,优化流水线性能,降低流水线设计复杂度。对于乘法类指令,采用3级流水硬件乘法器,完成乘法需要3周期,以此来提高系统时钟频率。针对除法指令,采用多周期完成的除法算法,在面积与速度上取得均衡。
[Abstract]:In twenty-first Century, SoC (System on Chip, on chip system) has been developed rapidly. As the core microprocessor of SoC, the microprocessor plays a more and more important role in every application field. Embedded microprocessor has a wide application in industrial control, personal consumption electronics, communication, military industry, and most of the SoC chips are used in ARM architecture, A The embedded microprocessor of RM's ARM architecture has occupied most of the market share in the embedded market.
This paper studies the Cortex-M3 processor of ARM Cortex-M series, and designs an embedded microprocessor which is fully compatible with the Cortex-M3 instruction set. It has the characteristics of high primary frequency and low power consumption.
First, based on the three level pipelining of Cortex-M3 processor, the 3 stage pipelined Execution phase is divided into Execution, Memory Access, and Write Back to reduce the key delay of Execution, and it is extended to the 5 level pipeline to improve the main frequency and improve the performance of the micro processor.
Secondly, gate gating technology is added to the processor soft core to reduce the power consumption of the processor.
Finally, by using the Harvard bus structure and double write mechanism, the data throughput is improved, the pipelining performance is optimized and the pipeline design complexity is reduced. For the multiplication class instruction, the 3 level pipelining hardware multiplier is used to complete the multiplication of 3 cycles to improve the clock frequency rate. Method, equalizing the area and speed.

【学位授予单位】：南京理工大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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