宽电压SRAM时序控制电路的研究与实现

发布时间：2018-04-22 19:40

本文选题：静态随机存取存储器 + 宽电压　；参考：《东南大学》2016年硕士论文

【摘要】：近年来,随着移动互联网设备的快速普及,对移动处理器性能和功耗的要求越来越高,动态电源电压调节技术很好的实现了这两个优点。但是作为移动处理器的重要组成模块：静态随机存取存储器(Static Random Access Memory, SRAM),当其工作在宽电压时,其时序控制电路的设计存在着两个重要问题：一、低电压下局部工艺变化增大导致时序电路的延迟变化增大,增大了关键路径延迟,降低芯片性能；二、由于传统时序电路对电压的跟踪性不佳,当电压高低变化时,SRAM出现读错误。针对这两个问题,本文首先研究了时序控制电路对SRAM读关键路径的影响,对时序控制电路在宽电压下工作时受工艺变化的影响做了分析,同时详细调研了传统时序控制电路及现有的几种改进的时序控制电路。然后提出了一种抗工艺变化的宽电压复制位线技术,该技术分为两部分电路：一、采用并行放电的局部复制位线技术,有效减少了低电压下局部工艺变化带来的时序电路延迟变化,相比现有的复制位线技术,该技术不增加任何额外延迟,提高了读性能；二、采用基于BIST测试的可调延迟的分级复制位线技术,通过在不同电压下分别调节复制位线的放电单元数目,使时序电路在宽电压范围内都有最优的输出延迟,实现了对电压的跟踪,相比传统采用可调反相器链来调节延迟的方法,该方案有着更好的温度跟踪性,同时不需要额外的版图面积。基于SMIC 40nm CMOS工艺,本文参与完成了一款64Kbits的宽电压SRAM设计,负责完成时序控制模块设计。通过仿真和测试,结果表明：本文设计的SRAM时序电路,相比传统时序电路,在0.6V下延迟变化减小了71%；采用本文设计,相比传统SRAM,在0.6V下,整体SRAM的读延时减小了17.2%。
[Abstract]:In recent years, with the rapid popularization of mobile Internet devices, the performance and power consumption of mobile processors are becoming more and more high. Dynamic power supply voltage regulation technology has realized these two advantages. However, as an important component of mobile processor, static Random Access memory (SRAMU) has two important problems in the design of sequential control circuit when it works at wide voltage. The increase of local process changes at low voltage leads to the increase of the delay of sequential circuits, which increases the critical path delay and reduces the chip performance. Secondly, because of the poor voltage tracking performance of the traditional sequential circuits, A reading error occurs in the SRAM when the voltage varies. Aiming at these two problems, this paper first studies the influence of sequential control circuit on the critical path of SRAM reading, and analyzes the influence of the process change when the sequential control circuit works at wide voltage. At the same time, the traditional sequential control circuit and several existing improved sequential control circuits are investigated in detail. Then, a wide voltage copy bit line technique is proposed to resist process change. The technology is divided into two parts: one is partial replication bit line technique, which is based on parallel discharge. It can effectively reduce the delay changes of sequential circuits caused by local process changes at low voltage. Compared with the existing replication bit line technology, this technology does not increase any additional delay and improves read performance. By adjusting the number of discharge units at different voltages, the timing circuits have optimal output delay in a wide voltage range by adopting a hierarchical replica bit line technique based on BIST test, which can adjust the discharge number of the duplicated bit lines at different voltages. The voltage tracking is realized. Compared with the traditional method of adjusting the delay with adjustable inverters, this method has better temperature tracking performance and does not require extra layout area. Based on SMIC 40nm CMOS process, this paper completes a wide voltage SRAM design of 64Kbits, which is responsible for the design of timing control module. The results of simulation and test show that compared with the traditional sequential circuits, the delay variation of the SRAM sequential circuit is reduced by 71V, and the reading delay of the whole SRAM is reduced by 17.2V compared with the traditional SRAM.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TP333

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