可重构FFT和Viterbi协处理器的研究与实现

发布时间：2018-04-25 04:40

本文选题：软件无线电 + 可重构　；参考：《国防科学技术大学》2013年硕士论文

【摘要】：本文以软件无线电为背景,重点着眼于其可重构特性。结合数字通信系统中常用的FFT算法和Viterbi译码算法,通过分析FFT算法和Viterbi译码算法的运算过程,找到两个算法结构上的相似之处,据此提出新的可重构的蝶形计算单元。在可重构蝶形计算单元的基础之上,提出了可重构的FFT和Viterbi协处理器。主要贡献包括:1.针对传统数字通信系统中FFT算法和Viterbi译码算法单独实现,硬件资源开销过大,不能很好地满足软件无线电灵活性要求的情况,结合软件无线电的可重构需要,提出将FFT算法和Viterbi译码算法用一个可重构的硬件结构实现,达到了节省硬件开销,增强硬件灵活性的目的。2.通过分析FFT算法和Viterbi算法的运算过程,找到两个算法运算过程中的共同点,并在此基础之上实现了可重构的蝶形计算单元。该可重构蝶形计算单元所需硬件资源,相对于分立实现的FFT算法和Viterbi译码算法的蝶形计算单元要少三分之一左右。3.在可重构的蝶形计算单元基础之上,提出了可重构的FFT和Viterbi协处理器。该处理器不但可以在FFT算法和Viterbi算法之间切换,而且在FFT算法的实现上也实现了4点到1024点之间的可变点数的计算,Viterbi译码算法在码率、约束长度以及生成函数都是在一定范围内可配置的。
[Abstract]:This paper focuses on the reconfigurable characteristics of software radio. Combined with FFT algorithm and Viterbi decoding algorithm commonly used in digital communication system, by analyzing the operation process of FFT algorithm and Viterbi decoding algorithm, the similarities between the two algorithms are found, and a new reconfigurable butterfly computing unit is proposed. On the basis of reconfigurable butterfly computing unit, reconfigurable FFT and Viterbi coprocessors are proposed. The main contributions include: 1. In the traditional digital communication system, the FFT algorithm and the Viterbi decoding algorithm are implemented separately, and the hardware resources are too expensive to meet the flexible requirements of software radio. The reconfigurable requirements of software radio are combined. The FFT algorithm and the Viterbi decoding algorithm are implemented with a reconfigurable hardware structure, which can save the hardware cost and enhance the flexibility of the hardware. By analyzing the operation process of FFT algorithm and Viterbi algorithm, the common points of the two algorithms are found, and the reconfigurable butterfly computing unit is realized on this basis. The hardware resource of the reconfigurable butterfly computing unit is about 1/3 less than that of the discrete FFT algorithm and the Viterbi decoding algorithm. Reconfigurable FFT and Viterbi coprocessors are proposed on the basis of reconfigurable butterfly computing units. The processor can not only switch between FFT algorithm and Viterbi algorithm, but also realize the calculation of variable points from 4 points to 1024 points in the implementation of FFT algorithm. The constraint length and the generating function are configurable in a certain range.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332;TN92

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