高性能嵌入式处理器的FPGA验证

发布时间：2018-04-29 17:54

本文选题：FPGA验证 + 嵌入式处理器　；参考：《上海交通大学》2014年硕士论文

【摘要】：随着科技进步与发展，嵌入式处理器的应用日益广泛，设计规模和复杂度也飞速增长。FPGA相关技术的快速发展，为嵌入式处理器的功能验证提供技术基础。本文旨在完成一款高性能嵌入式处理器FPGA验证工作。本文首先对相关内容进行研究，包括嵌入式处理器结构、芯片设计流程、功能验证方法、FPGA验证关键步骤、FPGA结构和资源等。然后，基于一款高性能CPU内核，提出并实现一款嵌入式处理器系统的硬件设计。利用丰富的FPGA资源，设计一个结构简单、灵活通用的FPGA验证平台。在代码设计阶段开始搭建验证的基本系统，提前开始FPGA验证和软件开发，提高验证效率，增加验证可靠性和验证平台利用率。本文具体阐述了验证平台的实现过程。首先分析需求选择可行方案，，然后介绍代码移植过程，最后阐述基本系统搭建过程。以CPU核和DDR3测试为例介绍具体验证过程。在验证过程中，采用提前建立FPGA原型库、脚本批量调用和修改代码、使用多种调试方法等，努力提高可重用性和自动化程度，减少人为错误、提高工作效率。采用“模块级——系统级——应用级”递进式验证步骤，运行操作系统和测试程序，实现功能验证目标。验证结果表明验证平台合理可靠、灵活通用，验证效率高。最后，对主要工作进行总结。
[Abstract]:With the progress and development of science and technology, embedded processors are increasingly widely used, and the design scale and complexity are also growing rapidly. The rapid development of FPGA related technologies provides a technical basis for the functional verification of embedded processors. The purpose of this paper is to complete the FPGA verification of a high performance embedded processor. At first, this paper studies the related contents, including embedded processor structure, chip design flow, function verification method, FPGA verification key steps, FPGA structure and resources, and so on. Then, based on a high performance CPU kernel, the hardware design of an embedded processor system is proposed and implemented. Using abundant FPGA resources, a simple and flexible FPGA verification platform is designed. At the stage of code design, the basic system of verification is built, FPGA verification and software development are started in advance, the efficiency of verification is improved, the reliability of verification and the utilization rate of verification platform are increased. This paper describes the implementation process of the verification platform. This paper first analyzes the requirements of selecting feasible solutions, then introduces the process of code transplantation, and finally describes the process of building the basic system. Taking CPU kernel and DDR3 test as examples, the concrete verification process is introduced. In the process of verification, FPGA prototype library is built ahead of time, script batch calls and modifies code, and many debugging methods are used to improve reusability and automation, reduce human error and improve work efficiency. The function verification goal is realized by using the progressive verification step of "module level-system level-application level", running the operating system and testing program. The verification results show that the verification platform is reasonable and reliable, flexible and universal, and has high verification efficiency. Finally, the main work is summarized.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP332

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