基于FPGA的32位RISC微处理器的设计与实现

发布时间：2018-04-29 18:50

本文选题：MIPS + 微处理器　；参考：《河北工业大学》2012年硕士论文

【摘要】：基于RISC架构的MIPS指令兼容处理器是通用高性能处理器的一种。其架构简洁，运行效率高，在高性能计算，嵌入式处理，多媒体应用等各个领域得到了广泛应用。基于FPGA的微处理器设计具有易于调试，便于集成的特点。在片上系统设计方法日趋流行的趋势下，掌握一套复杂的微处理器设计技术十分必要。论文首先概述了MIPS指令集的重要特征，为讨论微处理器的具体设计奠定基础。本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令，解决了大部分数据相关，结构相关，乘除法的流水化处理等问题。文章的主体部分首先详细描述了处理器各个独立功能模块的设计，为后续的整体设计实现提供逻辑功能支持。随后按照指令执行过程中需经历的五个阶段，详细描述了微处理器中各阶段的逻辑设计。为了提高微处理器的工作效率，在微处理器设计实现的基础上，深入研究了流水线技术及相关问题的解决方法，改进了传统5级流水线结构，并基本解决了数据相关、结构相关和控制相关的问题。在完成了微处理器的整体逻辑设计后，借助EDA工具对微处理器的工作状态进行了软件仿真，给出仿真结果，仿真波形验证了微处理器的工作符合预想。最后用EDA工具对设计代码综合、实现，并下载到FPGA上，进行了简单的硬件验证。通过验证测试所得到的相关数据表明，论文所设计的32位微处理器满足设计要求，其最高时钟频率达到了12.376MHz。
[Abstract]:MIPS instruction compatible processor based on RISC architecture is a universal high performance processor. It has been widely used in many fields, such as high performance computing, embedded processing, multimedia application and so on. The design of microprocessor based on FPGA is easy to debug and easy to integrate. It is necessary to master a set of complex microprocessor design techniques under the trend of the increasing popularity of system design methods on a chip. Firstly, this paper summarizes the important features of MIPS instruction set, which lays a foundation for discussing the design of microprocessor. This design implements a standard 32-bit 5-stage pipeline MIPS instruction compatible CPU system. With more than 50 instructions in common use, the problems of data correlation, structural correlation and pipelining of multiplication and division are solved. In the main part of the paper, the design of each independent function module of processor is described in detail, which provides the logical function support for the following whole design. Then, according to the five stages of instruction execution, the logic design of each stage in microprocessor is described in detail. In order to improve the working efficiency of the microprocessor, based on the design and implementation of the microprocessor, the pipeline technology and the solution of related problems are studied in depth, the traditional 5-stage pipeline structure is improved, and the data correlation is basically solved. Structural and control-related issues. After the whole logic design of the microprocessor is completed, the software simulation of the working state of the microprocessor is carried out with the help of EDA tool, and the simulation results are given. The simulation waveform verifies that the work of the microprocessor is in accordance with the expectation. Finally, the design code synthesis, implementation, and download to FPGA with EDA tools, a simple hardware verification. The data obtained from the verification test show that the 32-bit microprocessor designed in this paper meets the design requirements, and its highest clock frequency reaches 12.376MHz.
【学位授予单位】：河北工业大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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