基于背板系统的PCI Express传输链路设计与SI仿真技术研究

发布时间：2018-04-29 20:17

本文选题：PCI + Express　；参考：《国防科学技术大学》2012年硕士论文

【摘要】：机架式背板系统由于其在性能上的高容量交换能力和卓越的稳定性成为复杂电子系统的主流构架，，是当今电信交换设备、高性能计算机等大型数字系统设计实现的基础。PCI Express作为第三代I/O总线技术的典型代表，以其通道数多、带宽高、兼容性好等性能受到业界的广泛应用与支持。但也正是因为PCI Express高速率、高带宽，尤其PCI Express3.0的传输速率达8Gbps，给电子系统设计师带来了跨背板传输的设计难题，即如何能有效地减小或者避免高速信号经过长距离传输所发生的诸如信号反射/衰减、介质损耗、抖动及码间干扰等信号完整性（SI）问题。本文结合工程实际需求，搭建了基于背板的实验系统，针对PCI Express的传输链路进行建模、设计和SI仿真，并对仿真结果进行详细地分析与研究。主要研究内容和成果包括以下几个方面：针对第三代I/O总线技术的发展，深入剖析了PCI Express的总线结构与协议，重点研究分析了PCI Express3.0各协议层的特点、编码方式，为后续PCI Express链路设计与SI仿真打下基础。针对高速PCB设计技术展开研究，对高速传输链路中的各关键要素（包括叠层、板材、过孔、连接器等）逐一进行分析、设计和SI仿真，尤其是分析了各个要素对高速信号传输的影响，并在分析仿真基础上对关键要素的参数进行设计优化，为后续实际工程设计做出了有益的尝试。针对本课题的设计目标，分析了多种机架式背板系统的结构及其特点，设计搭建了基于平行背板结构的实验系统。根据实验系统的互连模式，构建了跨背板的PCI Express高速信号传输链路模型。针对工程设计的实际需求，运用实验系统的高速信号传输链路模型，开展了对不同速率（5Gbps和8Gbps）条件下多种板材（FR4和N4000-13SI）、多种传输距离（55cm、80cm和100cm）的SI仿真分析。通过对PCI Express2.0与PCI Express3.0两种速率信号的跨背板传输进行全面仿真与分析，得出工程设计的可传输的设计距离。另外，为进一步改善背板信号的传输质量，提出了可在传输链路中增加中继芯片来增加背板的传输距离的设计方法，并进行了具有中继芯片的链路仿真分析。最后，本文针对未来所面临的14Gbps速率的背板设计进行仿真与讨论。
[Abstract]:Because of its high capacity and excellent stability, the frame backplane system has become the mainstream framework of complex electronic systems, and it is the telecommunication switching equipment nowadays. As a typical representative of the third generation of I / O bus technology, the design and implementation of large digital systems such as high-performance computers have been widely used and supported by the industry for its many channels, high bandwidth and good compatibility. But it is also because of the high speed and bandwidth of PCI Express, especially the 8Gbpss transmission rate of PCI Express3.0, which brings the electronic system designers the design problem of trans-backplane transmission. That is, how to effectively reduce or avoid the signal integrity problems such as signal reflection / attenuation, dielectric loss, jitter and inter-symbol interference (ISI) caused by long distance transmission of high speed signals. In this paper, an experimental system based on backplane is built to model, design and simulate the transmission link of PCI Express. The simulation results are analyzed and studied in detail. The main research contents and results include the following aspects: In view of the development of the third generation I / O bus technology, the bus structure and protocol of PCI Express are deeply analyzed, and the characteristics and coding methods of each protocol layer of PCI Express3.0 are emphatically studied, which lays a foundation for the design and SI simulation of subsequent PCI Express links. Based on the research of high speed PCB design technology, the key elements of high speed transmission link (including stack, plate, hole, connector, etc.) are analyzed one by one, and the design and SI simulation are carried out. In particular, the influence of various factors on high-speed signal transmission is analyzed, and the parameters of key elements are designed and optimized on the basis of analysis and simulation, which makes a useful attempt for the subsequent practical engineering design. Aiming at the design goal of this paper, the structure and characteristics of various machine frame backplane systems are analyzed, and the experimental system based on parallel backplane structure is designed and built. According to the interconnection mode of the experimental system, the PCI Express high-speed signal transmission link model across the backplane is constructed. In order to meet the practical requirements of engineering design, the SI simulation analysis of FR4 and N4000-13SISi, multiple transmission distances (55cm-1, 80cm and 100cm) under different rates (5Gbps and 8Gbpss) is carried out by using the high-speed signal transmission link model of the experimental system. Based on the simulation and analysis of the transmission of PCI Express2.0 and PCI Express3.0 signals across the backplane, the transmissible design distance of the engineering design is obtained. In addition, in order to further improve the transmission quality of backplane signal, a design method is proposed to increase the transmission distance of backplane by adding the relay chip to the transmission link, and the link simulation analysis with the relay chip is carried out. Finally, this paper simulates and discusses the design of 14Gbps rate backplane in the future.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP336

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