高速低功耗嵌入式SRAM的设计

发布时间：2018-05-08 12:13

本文选题：SRAM + 逻辑努力　；参考：《华中科技大学》2012年硕士论文

【摘要】：SRAM（Static Random Access Memory）是SOC（System On Chip）中最为常见的模块之一，随着工艺的进步，片上SRAM的速度和容量都取得了飞速的发展。大容量的SRAM势必会带来更多的功耗开销，因而高速、大容量、低功耗SRAM的设计是当今研究的热点和难点。本文结合实际应用需求，，采用自底向上的层次化方法，设计了一个全定制8K×32b的SRAM。从SRAM最基本的存储单元开始，依据当前SRAM存储单元存在的几种方案，对比分析选定了适合本课题的6管存储单元。同时，为了降低功耗，采用字线分割技术将存储阵列划分为4块。采用了预译码和分块译码技术设计SRAM的译码电路可以提高译码速度并降低面积开销；门控时钟技术可以进一步降低系统功耗；精心设计的预充电路可以减小预充电的等待时间。最后为了精确控制灵敏放大器的开启时间，降低工艺和外界因素对其的影响，避免位线放电过多，本文采用改进的replica bitline结构来控制灵敏放大器的使能信号，因而可以较为准确的控制位线放电，使位线放电到100mV左右的电压差时开启灵敏放大器。本文设计的256Kb SRAM电路采用SMIC0.18m CMOS工艺在Cadence Virtuso平台下完成全定制设计，并采用Nanosim对SRAM整体电路进行仿真验证。和Memory Complier自动生成的SRAM相比，在TT工艺角下，本文设计的SRAM读取延时为2.095ns，比前者快0.5ns左右；平均功耗为10.53mW，约为前者的八分之一。因此本文设计的SRAM非常适合应用于低功耗、高速SOC中。本文独创性的工作包括：采用逻辑努力方法设计了一种高速译码电路；分析指出传统replica bitline结构可能存在反馈震荡的问题，并通过仿真证实了这些问题的存在；结合replica bitline结构提出了一种改进的replica bitline结构来解决传统replicabitline结构存在的问题，并仿真验证了改进的replica bitline电路；采用字线分割技术和分块技术将存储阵列分为4块，不仅降低了字线负载电容、加快读取速度，而且分块结构可以只激活选中的存储块，这样可以大大降低存储器的功耗。
[Abstract]:SRAM(Static Random Access memory is one of the most common modules in SOC(System on chip. With the development of technology, the speed and capacity of SRAM on chip have been developed rapidly. Large capacity SRAM is bound to bring more power consumption overhead, so the design of high speed, large capacity and low power SRAM is a hot and difficult point. In this paper, a fully customizable 8K 脳 32b SRAM is designed by using the bottom-up hierarchical method combined with the practical application requirements. Starting from the most basic memory cell of SRAM, according to several schemes of current SRAM storage cell, the 6 tube memory cells suitable for this subject are selected by comparison and analysis. At the same time, in order to reduce power consumption, the memory array is divided into 4 blocks using word line segmentation technology. Using predecoding and block decoding techniques to design the decoding circuit of SRAM can improve the decoding speed and reduce the area overhead; the gating clock technology can further reduce the power consumption of the system; and the carefully designed precharging circuit can reduce the waiting time of precharging. Finally, in order to accurately control the opening time of the sensitive amplifier, reduce the influence of process and external factors on it, and avoid excessive bit line discharge, an improved replica bitline structure is used to control the enabling signal of the sensitive amplifier. Thus, the bit line discharge can be controlled accurately, and the sensitive amplifier can be turned on when the bit line discharge to the voltage difference about 100mV. The 256Kb SRAM circuit designed in this paper uses SMIC0.18m CMOS process to complete the full customization design under the Cadence Virtuso platform, and Nanosim is used to simulate the whole SRAM circuit. Compared with SRAM generated automatically by Memory Complier, the read delay of SRAM designed in this paper is 2.095ns, which is faster than that of SRAM generated automatically by Memory Complier, and the average power consumption is 10.53mW, which is about 1/8 of the former. Therefore, the SRAM designed in this paper is very suitable for low power consumption and high speed SOC. The original work of this paper includes: designing a high speed decoding circuit by using logical effort method, analyzing and pointing out that the traditional replica bitline structure may have the problem of feedback oscillation, and validating the existence of these problems by simulation. Combined with replica bitline structure, an improved replica bitline structure is proposed to solve the problems existing in traditional replicabitline structure, and the improved replica bitline circuit is verified by simulation, and the memory array is divided into 4 blocks by word line segmentation and block dividing technology. Not only the load capacitance of the word line is reduced and the read speed is accelerated, but also the block structure can only activate the selected memory block, which can greatly reduce the memory power consumption.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TN47;TP368.1

【参考文献】