YHFT-Matrix处理器中EMIF与DDR2接口的设计与实现

发布时间：2018-05-08 19:13

本文选题：YHFT-Matrix + 外部存储器接口　；参考：《国防科学技术大学》2012年硕士论文

【摘要】：YHFT-Matrix处理器是国防科技大学设计的一款高性能DSP，主要面向3GPP-LTE无线通信基带处理领域。采用VLIW结构，16/32位可变长类RSIC指令集，每周期最大流出10条指令。处理器包含标量和向量两部分运算单元，标量单元负责简单的计算以及程序流控，向量单元内含有多个向量运算部件，提供主要的运算能力。现今运算能力的大幅提高对存储器的数据传输速率有了更高的要求。为了设计出更高性能的外部存储器接口（EMIF）部件，本文从研究DDR2存储器的结构和时序特点入手，并根据YHFT-Matrix处理器的体系结构设计出一款能够同时处理四核访问请求的EMIF。同时兼顾DDR2SDRAM和ASRAM的结构特点，，完成了适用于本款高性能DSP的EMIF设计、验证与测试，DDR2SDRAM的连接与板级测试。针对YHFT-Matrix处理器内部数据通路结构，提出了EMIF模块对各请求源进行轮转式仲裁、根据优先级排序，并将通信协议转换成AXI总线的协议的设计方法。最终使得12个请求源能够公平的访问外存。在协议转换时，由于外部存储器与内核时钟频率不同，本文设计了一个异步对接，负责将500Mhz时钟域下的内核信号同步到DDR2SDRAM采用的200Mhz时钟域。在完成验证与测试之后，本文对EMIF的传输方式又做了部分修改，使得传输效率有了大幅提升。采用了将DDR2控制器（固核）和PHY（硬核）集成到YHFT-Matrix处理器内的连接策略，并深入分析了YHFT-Matrix处理器中的DDR2接口。DDR2接口可以外接4个16-bit位宽的1Gbit器件组成4Gbit的DDR2存储器。DDR2PHY的时钟达200Mhz，数据宽度为64位。DDR2控制器对芯片内部提供AXI数据总线和APB配置总线接口，并负责为指令Cache、数据Cache和DMA（直接存储器访问接口）提供程序和数据。DDR2SDRAM通过EMIF模块与处理器内核连接起来。此外，本文对以上设计进行了较为系统地验证，并进行了板级测试。测试结果表明，单核得到DDR2SDRAM读每个字最短时间为15ns，写一个字最短时间为10ns，四核同时读的情况也可维持单核的15ns一个字。在优化后，单核DMA读速率有了接近50%的提高，但四核同时读的速率并没有显著提高。
[Abstract]:YHFT-Matrix processor is a high performance DSP designed by the University of National Defense Science and Technology. It is mainly oriented to the baseband processing field of 3GPP-LTE wireless communication. A 16 / 32 bit variable length RSIC instruction set with VLIW structure is used, with a maximum outflow of 10 instructions per cycle. The processor consists of scalar unit and vector unit. Scalar unit is responsible for simple calculation and program flow control. Nowadays, the great improvement of computing power requires higher data transmission rate of memory. In order to design a higher performance external memory interface (EMIF) component, this paper studies the structure and timing characteristics of DDR2 memory, and designs an EMIF which can process four-core access requests simultaneously according to the architecture of YHFT-Matrix processor. At the same time, considering the structural characteristics of DDR2SDRAM and ASRAM, the design of EMIF suitable for this high performance DSP is completed, and the connection and board test of DDR2 SDRAM are verified and tested. Aiming at the internal data path structure of YHFT-Matrix processor, this paper presents a design method for EMIF module to rotate each request source, sort it according to priority, and convert the communication protocol to AXI bus. Finally, 12 request sources can access the external memory equitably. In the protocol conversion, because the external memory and the kernel clock frequency are different, this paper designs an asynchronous docking, which is responsible for synchronizing the kernel signals in the 500Mhz clock domain to the 200Mhz clock domain adopted by DDR2SDRAM. After completing the verification and testing, the transmission mode of EMIF is partly modified in this paper, which greatly improves the transmission efficiency. The connection strategy of integrating DDR2 controller (fixed core) and PHY (hard core) into YHFT-Matrix processor is adopted. The DDR2 interface. DDR2 interface in YHFT-Matrix processor can be connected with four 1Gbit devices with 16-bit width to form 4Gbit DDR2 memory. DDR2PHY clock is 200Mhz. the data width is 64 bits. DDR2 controller provides AXI data bus and APB configuration bus interface to the chip. It is also responsible for providing programs and data. DDR2 SDRAM for instruction Cache. data Cache and DMA (Direct memory access Interface). The SDRAM is connected to the processor kernel through the EMIF module. In addition, the above design is systematically verified and tested at board level. The test results show that the minimum time for DDR2SDRAM to read each word is 15ns, and the shortest time for writing a word is 10ns.The four-core simultaneous reading can also maintain a single core 15ns word. After optimization, the reading rate of mononuclear DMA was increased by nearly 50%, but the rate of simultaneous reading by four cores was not significantly increased.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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