片上系统PLB总线及其相关模块的设计与验证

发布时间：2018-05-12 02:17

本文选题：SoC + PLB总线　；参考：《西安电子科技大学》2013年硕士论文

【摘要】：总线及其接口的效率决定了SoC系统的效率，低效率的总线不仅影响系统之间各个模块的通信性能，削弱系统的性能，而且会占用大量本来就有限的片上系统资源。PLB总线是IBM开发的CoreConnect总线中的最重要组成部分。PLB总线的相关技术目前主要被国外大公司掌握着，为了研发自主知识产权的核心技术，并为今后的应用开发做铺垫，，本文对PLB总线做了工程研究。本文的工作主要是以PCI总线以及存储器作为从设备，设计出了符合要求的PLB总线接口以及总线控制模块。首先，分析比较市场上常见的五种总线规范，深入研究了PLB总线协议以及PLB总线接口的结构与机制。然后，在理解PLB总线时序以及本文内部各子模块的功能与工作机制的基础上，设计PLB总线模块、DMA模块、桥接器模块，并使用Verilog硬件描述语言实现这些模块的功能。最后，搭建PLB总线接口验证平台，提出了可行的验证策略，验证该系统的读写功能并分析结果。通过验证，证明本文所设计的PLB总线读写模块符合应用环境要求，能够完成读写功能。
[Abstract]:The efficiency of the bus and its interface determines the efficiency of the SoC system. The inefficient bus not only affects the communication performance of each module of the system, but also weakens the performance of the system. Moreover, it will occupy a large number of already limited on-chip system resources. PLB-bus is the most important component of CoreConnect bus developed by IBM. The related technology of CoreConnect bus is mainly controlled by large foreign companies at present. In order to develop the core technology of independent intellectual property rights, And for the future development of the application to do the groundwork, the PLB bus has done the engineering research in this paper. The main work of this paper is to design the PLB bus interface and bus control module with PCI bus and memory as slave device. Firstly, five common bus specifications in the market are analyzed and compared, and the structure and mechanism of PLB bus protocol and PLB bus interface are deeply studied. Then, on the basis of understanding the timing of PLB bus and the function and working mechanism of each sub-module in this paper, we design the PLB bus module and bridge module, and use Verilog hardware description language to realize the functions of these modules. Finally, the PLB bus interface verification platform is built, a feasible verification strategy is proposed, and the reading and writing function of the system is verified and the results are analyzed. Through the verification, it is proved that the PLB bus reading and writing module designed in this paper meets the requirements of the application environment and can complete the reading and writing function.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336

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