基于eDRAM的多核三维片上存储结构

发布时间：2018-05-12 03:06

  本文选题：多核 + 众核　； 参考：《国防科学技术大学》2013年硕士论文

【摘要】：多核是当前微处理器的发展潮流。随着工艺尺寸不断减小,单位面积内可集成的晶体管密度来越来越大,集成在单个片上的核数也越来越多。受到面积、功耗的制约,多核处理器在向众核千核方向扩展时,对存储系统的要求越来越高,如何构建延时更小、容量更大、带宽更大的片上存储结构成为发展众核千核处理器的关键问题。三维集成电路技术通过采用TSV通孔可将多个die堆叠在一个芯片上,从而提高集成度,减小芯片内互连延迟和功耗,可极大地扩展片上存储结构的设计空间。e DRAM技术采用逻辑兼容工艺可将DRAM单元集成在芯片上,比SRAM技术拥有更大存储密度,更低的功耗,在大容量下拥有更小的访问延迟,可用于构建片上高速大容量cache。结合三维集成电路技术和e DRAM技术,可有效地解决多核处理器在向众核千核处理器发展过程中面临的存储问题。本文介绍了常见的片上存储结构模型。CACTI是一款性能优良的存储器延迟、功耗、面积模拟器。本文利用改进后的CACTI 6.5研究了e DRAM cache的特性,提出了基于e DRAM的高度可扩展的存储模型HSCM2。Mc PAT是一款流行的多核处理器功耗、面积和时序模拟器。为了使之可以可更贴近实际处理器的设计,本文修改了Mc PAT,并利用修改的Mc PAT展开可扩展的多核众核片上存储模型M2SM2设计,并向三维进行了扩展,提出了两种3D M2SM2结构模型3D M2SM2-A和3D M2SM2-B。本文介绍了TSV的电气特性,提出了用于建模TSV的面积、功耗和时序模型。本文提出了一个简单的三维处理器模型,本文将Mc PAT修改为3D Mc PAT,添加了对三维处理器模型的支持。本文最后利用3D Mc PAT对两种3D M2SM2模型的面积、功耗展开了研究,指出采用更先进的工艺、使用硬件复杂度较低的核、采用e DRAM技术和三维集成电路技术、采用层次更多的片上存储结构是未来多核众核处理器的发展趋势。
[Abstract]:Multi-core is the current trend of microprocessor development. As the process size decreases, the number of cores integrated on a single chip increases with the increasing density of integrated transistors per unit area. Restricted by the area and power consumption, the multi-core processor demands more and more storage system when it expands to the multi-core thousand core, so how to build the memory system with less delay and larger capacity. More bandwidth on-chip memory architecture has become a key issue in the development of multi-core thousand-core processors. Three-dimensional integrated circuit technology can stack multiple die on a single chip by adopting TSV holes, so as to improve integration and reduce interconnect delay and power consumption. The design space. E DRAM, which can greatly expand the on-chip memory structure, can integrate DRAM cells on the chip with a logical compatible process, which has greater memory density, lower power consumption and smaller access latency under large capacity than SRAM technology. Can be used to build on-chip high-speed large-capacity cache. Combined with 3D integrated circuit technology and e DRAM technology, the storage problem faced by multi-core processors in the development of multi-core Thousand core processors can be effectively solved. This paper introduces the common on-chip memory architecture model. CACTI is a memory delay, power consumption, area simulator with good performance. In this paper, we use the improved CACTI 6.5 to study the characteristics of e DRAM cache, and propose a highly extensible storage model based on e DRAM, HSCM2.Mc PAT, which is a popular multi-core processor power, area and timing simulator. In order to make it more close to the design of real processor, this paper modified MC path, expanded the extensible multi-core storage model M2SM2 design by using modified MC PAT, and extended it to 3D. Two 3D M2SM2 models, 3D M2SM2-A and 3D M2SM2-B, are proposed. This paper introduces the electrical characteristics of TSV and presents an area, power and timing model for modeling TSV. In this paper, a simple 3D processor model is proposed. In this paper, the Mc PAT is modified to 3D MC processor, and the support for 3D processor model is added. Finally, using 3D MC PAT to study the area and power consumption of two 3D M2SM2 models, it is pointed out that using more advanced technology, using the kernel with lower hardware complexity, using e DRAM technology and 3D integrated circuit technology. It is the development trend of multi-core processor in the future to adopt more hierarchical on-chip memory structure.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333
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本文编号：1876832