一种超低功耗、容错的静态随机存储器设计

发布时间：2018-05-12 21:41

本文选题：静态随机存储器 + 亚阈值　；参考：《天津大学》2012年硕士论文

【摘要】：随着移动通信、生物医学和空间应用的不断发展,半导体数字系统呈现出低功耗的发展趋势。作为数字系统的重要组成部分之一的存储器,在低功耗方面受到了格外关注。然而,由于静态随机存储器(SRAM)亚阈值工作时,会降低静态噪声容限(SNM),这给亚阈值SRAM的设计带来了很大难度。在亚阈值电源电压下,传统的六管SRAM存储单元由于没有足够的噪声容限而不能很好的工作。为了在亚阈值工作下实现超低功耗,有研究机构指出通过采用读/写分开机制能够有效地解决静态噪声容限降低的问题。为了减轻单粒子效应的影响,提高并保持SRAM在亚阈值条件下工作的稳定性和低功耗的特性,本文设计了一款1K×8bits的超低功耗同步时序SRAM芯片,采用基于双互锁存储单元(DICE)结构的SRAM存储单元来消除传统DICE存储单元读操作时的缺陷。利用TSMC 90nm CMOS工艺对SRAM进行了仿真。仿真结果显示:当电源电压VDD为0.3V时,该SRAM工作频率最大可达到2.7MHz。此时,功耗仅为0.35μW;而当VDD为1V时,最大工作频率为58.2MHz,功耗为83.22μW。此外,本文设计的存储单元中晶体管数量比传统六管SRAM存储单元中晶体管数量多,因此单元面积有所增加。本课题主要完成了一款新的SRAM存储单元的设计,即在解决超低功耗和防辐射这两个问题的同时来完成大容量存储器的设计。
[Abstract]:With the development of mobile communication, biomedicine and space applications, semiconductor digital systems show a trend of low power consumption. As one of the most important components of digital system, memory has attracted much attention in low power consumption. However, when the static random access memory (RAM) sub-threshold is working, the static noise tolerance can be reduced, which makes the design of the sub-threshold SRAM very difficult. Under the subthreshold power supply, the traditional six-transistor SRAM memory cells can not work well because of the lack of sufficient noise tolerance. In order to achieve ultra-low power consumption under sub-threshold operation, some researchers have pointed out that the problem of static noise tolerance reduction can be effectively solved by using read / write separation mechanism. In order to reduce the effect of single particle effect and to improve and maintain the stability and low power consumption of SRAM under sub-threshold condition, a 1K 脳 8bits ultra-low power synchronous sequential SRAM chip is designed in this paper. The SRAM memory cell based on double interlock memory cell (DICE) is adopted to eliminate the defects of the traditional DICE memory cell read operation. SRAM is simulated by TSMC 90nm CMOS process. The simulation results show that when the supply voltage VDD is 0.3 V, the maximum operating frequency of the SRAM can reach 2.7 MHz. At this time, the power consumption is only 0.35 渭 W, while when VDD is 1 V, the maximum operating frequency is 58.2 MHz, and the power consumption is 83.22 渭 W. In addition, the number of transistors in the memory cells designed in this paper is more than that in the traditional six-transistor SRAM memory cells, so the cell area is increased. In this paper, a new SRAM memory cell is designed, which solves the two problems of ultra-low power consumption and radiation protection, and completes the design of mass memory at the same time.
【学位授予单位】：天津大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333.8

【相似文献】