基于FPGA的PCIe总线DMA平台设计

发布时间：2018-05-14 13:16

本文选题：LTE + PCI　；参考：《武汉理工大学》2013年硕士论文

【摘要】：随着通信技术的迅速发展,LTE应运而生,LTE系统具有网络时延减少、更高的用户数据速率、系统容量和覆盖的改善的优点,但缺点也明显：对带宽的要求,对传输速率的要求等都使得系统更复杂。传统的PCI,PCI_X等总线,因其性能无法达到系统的传输要求,正逐步淘汰,PCIe总线作为新一代的总线标准,它具有数据传输速率高,可更好地支持未来高端显卡等优点,在LTE系统的物理层中,设计基于PCIe总线DMA传输方式的数据通道平台可有效进行数据传输,减少了数据传输的瓶颈。并且PCIe总线具有良好的可扩展性,可通过对系统升级来实现更高数据传输速率的要求。本文设计的基于FPGA的PCIe总线DMA平台系统的设计有很重要的实际意义,它充分利用了PCIE总线的众多优点,解决了LTE系统中分布式基站的数据传输问题,为整个系统的实现打下了良好基础。本文的研究内容包含以下三部分：首先,深入研究了PCIe总线协议,剖析PCIe协议标准中三个层面的不同分工,在不同层面的数据传送包的不同格式下的不同功能。纵观LTE的发展状况,PCIe总线技术必成为主流。其次,在深入研究了PCIe协议的基础上,利用Xilinx公司的PCIe IP Core生成了系统所需的PCIe总线下的Endpoint模块,在Endpoint模块基础上,设计DMA模块,并针对本项目的要求设计接口模块。最后,编写测试模块,在Modelsim中对PCIe-DMA进行联合仿真,验证功能正确后,在ISE环境中进行板上调试。通过实际板卡测试,系统的DMA传输速度可稳定达到2Gbps,没有丢帧和误码现象,系统能够稳定运行,能达到LTE系统中分布式基站中传输功能模块的设计要求。本文的创新点是虚拟FIFO的设计,虚拟FIFO提供时钟域的交叉,可存储和转发大的数据包,解决了DDR3SDRAM直接读取写入低效率的问题。采用了虚拟FIFO使需要读取和写入的数据包在此重新打包,可大大的提高传输效率,并且FIFO与memory controller直接相连,可忽略memory controller的反应时间。
[Abstract]:With the rapid development of communication technology, LTE system has the advantages of reduced network delay, higher user data rate, improved system capacity and coverage. The requirement of transmission rate makes the system more complicated. Because the traditional PCI / PCIX bus can not meet the transmission requirements of the system, PCIe bus is being phased out as a new generation bus standard. It has the advantages of high data transmission rate and can better support the future high-end graphics card. In the physical layer of LTE system, the design of data channel platform based on PCIe bus DMA transmission mode can effectively carry out data transmission and reduce the bottleneck of data transmission. Moreover, PCIe bus has good expansibility and can achieve higher data transmission rate by upgrading the system. The design of PCIe bus DMA platform system based on FPGA in this paper is of great practical significance. It makes full use of the advantages of PCIE bus and solves the data transmission problem of distributed base station in LTE system. It lays a good foundation for the realization of the whole system. The research content of this paper includes the following three parts: Firstly, the PCIe bus protocol is deeply studied, the different division of labor in three layers of PCIe protocol standard is analyzed, and the different functions under different formats of data transfer packets at different levels are analyzed. Throughout the development of LTE, PCIe bus technology will become the mainstream. Secondly, based on the research of PCIe protocol, the Endpoint module based on PCIe bus is generated by the PCIe IP Core of Xilinx Company. The DMA module is designed on the basis of Endpoint module, and the interface module is designed according to the requirements of this project. Finally, the test module is written and the PCIe-DMA is simulated in Modelsim. After the function is correct, the test module is debugged in the ISE environment. Through the actual card test, the DMA transmission speed of the system can reach 2Gbps. there is no frame loss and error code phenomenon. The system can run stably and can meet the design requirements of the transmission function module in the distributed base station in the LTE system. The innovation of this paper is the design of virtual FIFO. Virtual FIFO provides the crossover of clock domain, can store and forward large packets, and solves the problem of low efficiency of DDR3SDRAM direct reading and writing. The virtual FIFO is used to repackage the data packets that need to be read and written, which can greatly improve the transmission efficiency, and the FIFO is directly connected with memory controller, and the memory controller reaction time can be ignored.
【学位授予单位】：武汉理工大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336;TN929.5

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