众核处理器的流水线紧耦合指令循环缓存设计

发布时间：2018-05-15 10:45

本文选题：循环缓存 + 众核处理器　；参考：《计算机研究与发展》2017年04期

【摘要】：能效比是未来高性能计算机需要解决的重要问题.众核处理器作为高性能计算机的重要实现手段,其微结构的优化设计对能效比提升尤为关键.提出了1种面向众核处理器的流水线紧耦合的指令循环缓存设计,以较小的L0指令缓存提供更加高能效的指令取指.作为体系结构研究同硬件可实现性紧密结合的1次尝试,设计始终考虑了硬件实现代价这一关键约束.为了控制L0指令缓存对流水线性能的影响,指令缓存采用了循环出口预取技术,以此保证指令缓存提供的低功耗的指令取指能够最终转化为流水线能效比的提升.在gem5模拟器上实现了对指令循环缓存的模拟.对SPEC2006的测试结果表明,在不影响流水线性能的前提下,设计的典型配置可以减少27%的指令取指功耗以及31.5%的流水线前段部件动态功耗.
[Abstract]:Energy efficiency ratio (EER) is an important problem to be solved by high performance computers in the future. As an important means of high performance computer, the optimization design of multi-core processor is very important to improve the energy efficiency ratio (EER). A pipelined tightly coupled instruction loop cache design for multicore processors is proposed to provide a more efficient instruction fetch with a smaller L0 instruction cache. As an attempt to closely combine architecture research with hardware realizability, the key constraint of hardware implementation cost is always considered in the design. In order to control the influence of L0 instruction cache on pipeline performance, cyclic exit prefetching technique is used in instruction cache to ensure that the low power consumption instruction fetch provided by instruction cache can be transformed into pipeline efficiency ratio. The instruction cycle cache is simulated on the gem5 simulator. The test results of SPEC2006 show that the typical configuration can reduce the power consumption by 27% and the dynamic power consumption by 31.5% without affecting the pipeline performance.
【作者单位】：数学工程与先进计算国家重点实验室;
【基金】：国家“八六三”高技术研究发展计划基金项目(2015AA01A301) 国家自然科学基金项目(91430214)~~
【分类号】：TP332

【相似文献】