64位流核心运算部件的设计与实现

发布时间：2018-05-15 21:04

本文选题：流处理器 + 流核心　；参考：《国防科学技术大学》2012年硕士论文

【摘要】：片上集成传统多核处理器（以桌面CPU为代表）和流多核处理器（以GPU为代表）已成为多核处理器的发展方向，但异构的结构导致功耗很大，分离的存储也会导致通信瓶颈，故本项目组提出同构通用流处理器的体系结构。该结构是由四个流核心共享前端构成一个流多核，根据应用程序来配置CPU和SP中流多核的数目。同构通用流处理器不仅要面向高性能计算应用，对图形图像处理也需要能快速处理，这些对处理器的运算部件提出了很高的要求。本课题完成了64位流核心运算部件的设计与实现，主要工作和创新点包括： 1、对于整数运算部件，充分利用图形图像处理的数据窄位宽的特性，完成了加/减法单元、乘法单元的设计，这两个运算单元与浮点运算共享前导零逻辑来灵活处理不同位宽运算，，从而有效利用资源，减少计算延迟。还完成了整数运算部件中比较单元、移位单元、除法单元的设计与VHDL代码实现。 2、对于浮点运算部件，完成了浮点加/减单元、浮点乘法单元、浮点/整数转换单元、浮点除法单元、浮点开方单元的设计与实现，并实现了浮点加/减、浮点乘法和浮点/整数转换操作的流水化设计，提升了浮点运算部件的处理能力。 3、利用Xilinx公司的ISE12.1开发软件，完成了64位流核心的系统验证平台设计。通过对各个运算单元添加测试激励来验证它们的功能正确性，通过系统执行多条浮点指令来验证流水化处理的正确性。验证的结果表明运算部件的设计实现了处理器要求的运算操作，并能够在整个流核心系统中正常运行。通过软件自动综合，得到了运算部件的相关性能参数。
[Abstract]:The integration of traditional multi-core processors (represented by desktop CPU) and stream multi-core processors (represented by GPU) has become the development direction of multi-core processors. However, heterogeneous architectures lead to high power consumption, and separate storage also leads to communication bottlenecks. Therefore, the project team proposes the architecture of the isomorphic universal stream processor. The structure is composed of four stream cores to share the front end, and the number of stream multicore in CPU and SP is configured according to the application program. The isomorphic general stream processor not only needs high performance computing applications, but also needs to be able to process graphics and images quickly. In this paper, the design and implementation of 64 bit stream core operation unit are completed. The main work and innovations are as follows: 1. For integer operation unit, the addition / subtraction unit and multiplication unit are designed by taking full advantage of the narrow bit width of graphics and image processing data. These two units share leading zero logic with floating-point operations to deal with different bit widths flexibly, thus effectively utilizing resources and reducing computational delays. The design of comparison unit, shift unit and division unit in integer operation unit and the implementation of VHDL code are also completed. 2. For the floating-point operation unit, the floating-point addition / subtraction unit, the floating-point multiplication unit, the floating-point / integer conversion unit, the floating-point division unit, the floating-point square unit are designed and implemented, and the floating-point addition / subtraction is realized. Floating-point multiplication and floating-point / integer conversion are pipelined to improve the processing power of floating-point operation components. 3. The system verification platform of 64 bit stream core is designed by using the ISE12.1 development software of Xilinx Company. Test incentives are added to each unit to verify their functional correctness, and the correctness of pipelining processing is verified by executing multiple floating-point instructions. The verification results show that the design of the computing unit realizes the operation required by the processor and can run normally in the whole stream core system. Through the automatic synthesis of the software, the related performance parameters of the operation parts are obtained.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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