协同式X86系统仿真中地址映射与指令译码技术研究

发布时间：2018-05-17 01:36

本文选题：系统仿真 + 协同式　；参考：《解放军信息工程大学》2013年硕士论文

【摘要】：随着微电子技术的快速发展，新型体系架构处理器不断涌现，应用软件资源稀缺问题凸显。将占市场主导地位的X86架构应用软件资源移植到新型处理器上，是实现新型处理器应用普及的有效途径。软硬件协同式X86系统仿真技术能够有效解决“代码移植”和体系结构兼容性的问题，通过引入适当硬件实现部分，使得软件部分和硬件部分协同工作，有效提升X86系统仿真性能，已成为新型处理器应用的重要支撑技术。本文深入分析制约X86系统仿真性能的关键瓶颈，对各仿真功能模块进行了软硬件划分，提出了软硬件协同式X86系统仿真模型，构建了以开源处理器OpenRISC平台为宿主机的X86系统仿真架构Co-AB。基于FPGA和OpenRISC SoPC平台，对Co-AB进行了测试与验证；设计并实现了HardTLB及其访问扩展指令，通过嵌入式汇编指令，使SoftMMU和HardTLB协同工作，提升了访存指令中虚实地址转换的仿真效率；提出了一种流水式指令译码仿真机制，设计并实现了流水式指令译码仿真部件，相对于指令串行译码仿真机制，有效减少了指令译码仿真的时间开销。实验测试结果表明，，本文所设计的协同式VMMU部件和流水式指令译码仿真部件能够正确地完成地址映射和指令译码仿真工作。协同式VMMU部件相比于传统软件实现方式可获得36.7%的访存性能提升；流水式译码机制相对于串行译码机制可以有效降低指令译码时间开销大约41.8%。
[Abstract]:With the rapid development of microelectronics, new architecture processors are emerging. It is an effective way to popularize the application of X86 architecture. Hardware / software co-X86 system simulation technology can effectively solve the problems of "code transplantation" and architecture compatibility. By introducing appropriate hardware implementation part, the software and hardware parts can work together. Improving the performance of X86 system simulation effectively has become an important supporting technology for new processor applications. In this paper, the key bottleneck that restricts the performance of X86 system simulation is deeply analyzed, the software and hardware of each simulation function module are divided, and the simulation model of hardware / software co-X86 system is proposed. An X86 system simulation architecture based on open source processor OpenRISC platform is constructed. Based on the platform of FPGA and OpenRISC SoPC, the Co-AB is tested and verified, and the HardTLB and its access extension instruction are designed and implemented. Through the embedded assembly instruction, SoftMMU and HardTLB work together, and the simulation efficiency of virtual address translation in memory access instruction is improved. A pipelined instruction decoding simulation mechanism is proposed. A pipelined instruction decoding simulation unit is designed and implemented. Compared with the instruction serial decoding simulation mechanism, the time cost of instruction decoding simulation is effectively reduced. The experimental results show that the cooperative VMMU part and the pipelined instruction decoding simulation unit designed in this paper can correctly accomplish the address mapping and instruction decoding simulation. Compared with the traditional software implementation, the cooperative VMMU module can achieve 36.7% memory access performance, and the pipelined decoding mechanism can effectively reduce the instruction decoding time cost about 41.8% compared with the serial decoding mechanism.
【学位授予单位】：解放军信息工程大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332;TP311.1

【参考文献】