基于65nm高性能SRAM关键电路的研究与设计

发布时间：2018-05-21 02:08

本文选题：高性能静态存储器 + 译码电路　；参考：《安徽大学》2013年硕士论文

【摘要】：随着移动互联网技术的发展,嵌入式处理器和片上系统(SoC, System on a Chip)的速度不断提高,从而推动高速缓存(Cache)对速度的需求,作为高速缓存的核心部件,静态随机存储器(SRAM, Static Random Access Memory)成为系统速度提升的关键。本文基于高性能嵌入式处理器的需求进行高速SRAM存储器的相关理论模型、结构优化和关键电路的研究,着重分析和改进现有高速SRAM的设计技术。高性能SRAM是指可以高速度工作的SRAM, SRAM的速度主要体现在地址输入到数据读出的延迟时间上,大小由从地址输入到数据读出的关键路径上延迟决定,包括地址输入缓冲、地址译码、字线选通、存储单元、位线输出、灵敏放大器及输出缓冲的延迟等,针对以上延迟模块,本文提出了一些优化SRAM速度的技术和电路结构,具体有： 1、对译码电路的互连线引入分布rC模型进行研究,结合工艺特性和传统延迟模型,合理考虑导线寄生特性的影响,为译码器电路的优化提供更精确的延迟模型。根据延迟优化的理论模型可确定SRAM存储器中译码电路的晶体管尺寸,从而实现高性能译码电路的设计及优化。 2、高性能SRAM存储器的核心部件是存储单元,通常存储单元决定了存储器的系统结构和稳定性。本文提出非对称六管存储单元,采用分级读操作形式,等比例增大读支路的3个管子尺寸,并采用低闽值晶体管,从而增大读支路的驱动强度。另外,由于线寄生影响越来越大,采用位线分级的读结构比较适合工艺进一步缩小的应用。 3、采用位线分级的方式可以提高大容量SRAM的工作速度,本文在传统位线分级的基础上,通过从位线放电快慢的角度分析,推导出更加优化的分级结构,可以减小位线电容,使得位线充放电更快,实现整体速度的提高。并在SMIC65nm工艺下设计了相应电路并进行仿真验证,从而论证了分析的正确性。通过上述分析研究,最终建立一套高性能SRAM存储器译码电路的延迟优化模型和设计方法,结合非对称六管存储单元和优化的位线分级技术,基于SMIC65nm LL (low leakage)工艺,设计了一款高性能4Kb SRAM存储器,经仿真验证当工作电压在1.2V时后仿真的访问时间为0.514ns,工作频率达到1.5GHz。
[Abstract]:With the development of mobile Internet technology, the speed of embedded processors and on-chip systems (SoC, System on a Chip) is increasing, which promotes the speed requirement of cache, which is the core component of cache. Static random access memory (SRAM) and Static Random Access Memory) are the key to improve the speed of the system. Based on the requirement of high performance embedded processor, this paper studies the theoretical model, structure optimization and key circuits of high speed SRAM memory, and focuses on analyzing and improving the existing design technology of high speed SRAM. High performance SRAM refers to the SRAM, which can work at high speed. The speed of SRAM is mainly reflected in the delay time between address input and data readout, and the size is determined by the delay in the critical path from address input to data readout, including address input buffering. Address decoding, word line gating, memory cell, bit line output, sensitive amplifier and output buffer delay, etc., this paper presents some techniques and circuit structures to optimize SRAM speed. 1. The distributed RC model is introduced into the interconnection of the decoding circuit. Combining the process characteristic and the traditional delay model, the influence of the parasitic characteristic of the conductor is considered reasonably, which provides a more accurate delay model for the optimization of the decoder circuit. According to the theoretical model of delay optimization, the transistor size of decoding circuit in SRAM memory can be determined, and the design and optimization of high performance decoding circuit can be realized. 2. The core component of high performance SRAM memory is memory cell, which usually determines the system structure and stability of memory. In this paper, an asymmetric six-transistor memory cell is proposed, in which the three-tube size of the reading branch is increased in equal proportion and the low threshold transistor is used to increase the driving strength of the reading branch. In addition, because of the increasing influence of line parasitism, the reading structure with bit line classification is more suitable for further reduction of technology. 3. The speed of large capacity SRAM can be improved by using bit line classification. Based on the traditional bit line classification, this paper deduces a more optimized classification structure from the angle of bit line discharge speed and slowness, which can reduce the bit line capacitance. Make bit line charge and discharge faster, achieve the overall speed of the increase. The corresponding circuit is designed and verified by simulation in SMIC65nm process, and the correctness of the analysis is proved. Through the above analysis and research, a set of delay optimization model and design method of high performance SRAM memory decoding circuit are established, combined with asymmetric six-transistor memory cell and optimized bit-line grading technology, based on SMIC65nm LL low leak process. A high performance 4Kb SRAM memory is designed. The simulation results show that the simulated access time is 0.514 ns and the operating frequency is 1.5 GHz when the working voltage is 1.2 V.
【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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