SDDR存储器:新型存储架构设计

发布时间：2018-05-21 07:20

本文选题：存储器 + DDR　；参考：《电光与控制》2014年06期

【摘要】：迄今为止,SDRAM存储器的扩容完全依赖于半导体工艺水平的升级,而提速取决于对时钟的利用方式。DDR3 SDRAM已达8倍速率,再提速已很困难。提出一种新型串行访问的SDDR存储器结构和片内串行只写总线,将DDR存储器封装成消息连接的构件,将访问存储器的命令、地址和数据等信息打成消息报包,经片内串行只写总线与构件化的DDR存储器交换信息。SDDR存储器减少了引脚,连接简单并且抗干扰能力强、可靠性高,易于扩容和进一步提升时钟速率,具有明显的实用前景。
[Abstract]:Up to now, the expansion of SDRAM memory depends entirely on the upgrading of semiconductor process level, and the speed up depends on the use of clock. DDR3 SDRAM has reached 8 times the rate, so it is very difficult to speed up again. A new type of serial access SDDR memory structure and on-chip serial write-only bus are proposed. The DDR memory is encapsulated into a message connection component, and the commands, addresses and data of the access memory are packed into a Sabbath packet. The exchange of information with component-based DDR memory via on-chip serial write-only bus reduces pin, easy connection, strong anti-interference ability, high reliability, easy to expand capacity and further increase clock rate, and has obvious practical prospects.
【作者单位】：太原理工大学信息工程学院;
【分类号】：TP333

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