USB接口软IP CORE代码设计及验证

发布时间：2018-05-22 18:54

  本文选题：USB + IP核　； 参考：《电子科技大学》2012年硕士论文

【摘要】：USB是英文(Universal Serial Bus)的缩写，中文就是通用串行总线。USB是Intel联合(Microsoft,IBM,康柏,NEC等)七家公司共同推出的总线标准，这是一种速度快、成本低、易于扩展的总线标准，同时也是目前电子产品中应用最为广泛的接口协议之一。支持设备即插即用和热插拔功能的USB总线标准的出现,对于信息产业和计算机的发展具有重大意义。鉴于USB广泛的应用及迅猛的发展和经济效益，本文设计了一个USB设备接口IP核,讨论了设计思想和方法。 本论文主要讨论了USB设备接口IP核的设计。根据复杂数字逻辑电路和系统设计思想,为了降低设计复杂度,经过深入研究USB协议后，决定在设计中采用自顶向下(Top-Down)的设计方法；同时该IP核使用VerilogHDL编写代码,在设计中我们把时序逻辑电路和组合逻辑电路分开设计，这样能够使得设计思路更清晰同时也让总体结构便于理解；为了使设计更易于综合，代码编写也必须遵循可综合风格并且注重跨时钟域的问题。论文主要包括以下几个方面： 1)首先学习和分析USB协议,分析协议标准和数据传输方式，根据学习到的协议内容和分析结果提出基于FPGA的USB设备接口IP核的总体设计方案，然后划分各功能模块,划分成五个模块:UTMI、控制器、物理层、FIFO、存储器接口和协议层。设计方案中最关键的三个模块是物理层模块、控制器模块和协议层模块。 2)用Verilog编写RTL级代码，完成各功能模块的详细设计。物理层模块主要完成采样异步数据流以及分离时钟和数据，模拟差分信号和数字信号的转换；控制器模块完成USB设备的数据传输和枚举；协议层模块功能比较复杂，为了实现复杂的USB协议，使用了有限状态机的设计方法，协议层主要完成数据的打包和解包等。 3)用ModelSim SE和QuartusⅡ软件对USB设备接口IP核进行综合仿真，对设备接口IP在FPGA硬件平台上进行了验证。在验证过程中，使用USB HOUND软件截取USB总线上的通信数据，然后对截取数据分析来验证USB主机和设备接口的数据通信是否成功。 验证结果表明，，该设计的USB设备接口IP核是符合USB协议规范要求的，能很好的实现USB数据通信的功能;如果想作为一个单独的IP模块嵌入到SoC系统设计中,还需要经过更深层次和更专业的优化,这里我们只讨论了功能的实现。
[Abstract]:USB (Universal Serial bus) is a bus standard developed jointly by seven companies, Intel, Microsoft, IBM, Compaq, etc., which is a fast, low cost and easy to extend bus standard. It is also one of the most widely used interface protocols in electronic products. The emergence of USB bus standard which supports plug and play and hot plug function is of great significance to the development of information industry and computer. In view of the wide application, rapid development and economic benefit of USB, this paper designs an IP core of USB device interface, and discusses the design ideas and methods. This paper mainly discusses the design of USB device interface IP core. According to the design idea of complex digital logic circuit and system, in order to reduce the design complexity, after deeply studying the USB protocol, it is decided to adopt Top-Downtop-down design method in the design, and the IP core uses VerilogHDL to write code. In the design, we separate the sequential logic circuit from the combinational logic circuit, which can make the design thinking clearer and the overall structure easier to understand; in order to make the design easier to synthesize, Code writing must also follow an integrated style and focus on cross-clock domains. The paper mainly includes the following aspects: 1) studying and analyzing the USB protocol, analyzing the protocol standard and data transmission mode, according to the protocol content and the analysis result, putting forward the overall design scheme of USB device interface IP core based on FPGA, then dividing each function module. Divided into five modules: UTMI, controller, physical layer FIFO, memory interface and protocol layer. The three key modules in the design are physical layer module, controller module and protocol layer module. 2) write RTL level code with Verilog, complete the detailed design of each function module. Physical layer module mainly completes sampling asynchronous data flow and separating clock and data, analog differential signal and digital signal conversion; Controller module completes data transmission and enumeration of USB device; Protocol layer module has complex function. In order to realize the complex USB protocol, the design method of finite state machine (FSM) is used, and the protocol layer mainly completes the data packaging and unpacking. 3) the IP core of USB device interface is simulated by ModelSim SE and Quartus 鈪

本文编号：1923235