基于FPGA的核间高速接口的设计与验证

发布时间：2018-05-24 05:43

本文选题：高速串行接口 + 千兆以太网　；参考：《电子科技大学》2014年硕士论文

【摘要】：随着用户对信息传输需求的不断增长,基带信号处理的处理带宽和吞吐量需求与日俱增。这对数据传输接口设计的要求越来越高,传统的并行传输技术并不能满足高带宽、高速率和高可靠性的需求。此时,高速串行传输技术应运而生,高速GTX接口和千兆以太网接口是其中两个重要的数据传输接口。基于片上网络(NoC)的多核处理器硬件设计规模和复杂程度不断增加,使得单片FPGA(或ASIC)硬件资源紧张的问题突出。此外并行化处理机制将一个大的处理任务划分为多个小的处理任务,分配到不同的处理器上分别运行,从而实现任务处理的并行化。这些都需要芯片间、处理器核间的高速数据传递。本论文利用高速串行接口实现了NoC互联扩展到多FPGA开发板的总体设计。首先介绍了高速GTX接口的传输技术。接着在高速串行传输接口设计部分,对Aurora协议和用户自定义通信协议进行分析,并对二者做了简要的比较。最后,结合设计需求,本文采用了用户自定义通信协议,并合理设计核间数据传输和状态采集这两种数据的帧格式,保证通道传输的可靠性与实时性。随着互联网技术不断地创新和进步,大量应用的需求使得以太网传输模式迅速发展,基于以太网的小型嵌入式通信系统的应用正变得越来越重要。千兆以太网作为第三代的以太网技术,不仅保持了原来传统以太网的优势,还具有许多新的特性,因此得到了广泛的应用。本文介绍了千兆以太网传输技术,对系统使用的PCS/PMA和三态MAC IP核进行了研究和软件仿真,完成了IP的设置和接口的设计。在验证平台上进行FPGA间、PC与FPGA间通过千兆以太网接口通信的实验测试时,首先通过FPGA间的通信验证了接口代码的正确性;再对通过BCM5396千兆以太网交换芯片连接FPGA和PC的场景进行了测试,通过查看寄存器信息调试实现PC与FPGA间的正常通信。最后,在Xilinx Kirtex-7系列FPGA芯片为核心的硬件平台上,完成了面向LTE公共基带处理应用的NoC原型实现,对本文所设计的各个高速接口的功能和性能进行了测试和验证。
[Abstract]:With the increasing demand of users for information transmission, the processing bandwidth and throughput of baseband signal processing are increasing. The traditional parallel transmission technology can not meet the requirements of high bandwidth, high speed and high reliability. At this time, high speed serial transmission technology came into being, high speed GTX interface and gigabit Ethernet interface are two important data transmission interfaces. The hardware design scale and complexity of multi-core processors based on on-chip network (NOC) are increasing, which makes the problem of single FPGA (or ASIC) hardware resource shortage prominent. In addition the parallel processing mechanism divides a large processing task into several small processing tasks and distributes them to different processors to realize the task processing parallelization. These require high-speed data transfer between chips and between processor cores. In this paper, a high-speed serial interface is used to realize the overall design of NoC interconnection to multi-FPGA development board. Firstly, the transmission technology of high speed GTX interface is introduced. Then, in the design of high-speed serial transmission interface, the paper analyzes the Aurora protocol and user-defined communication protocol, and makes a brief comparison between the two protocols. Finally, according to the design requirements, this paper adopts user-defined communication protocol, and reasonably designs the frame format of data transmission and state acquisition between cores to ensure the reliability and real-time of channel transmission. With the continuous innovation and progress of Internet technology, the demand of a large number of applications makes the Ethernet transmission mode develop rapidly. The application of small embedded communication system based on Ethernet is becoming more and more important. Gigabit Ethernet, as the third generation Ethernet technology, not only maintains the advantages of traditional Ethernet, but also has many new features, so it has been widely used. The transmission technology of gigabit Ethernet is introduced in this paper. The PCS/PMA and three-state MAC IP cores used in the system are studied and simulated, and the IP configuration and interface are designed. When we test the communication between FPGA PC and FPGA via Gigabit Ethernet interface on the verification platform, the correctness of the interface code is verified by the communication between FPGA and PC. The scene of connecting FPGA and PC through BCM5396 gigabit Ethernet switch chip is tested, and the normal communication between PC and FPGA is realized by checking register information. Finally, on the hardware platform of Xilinx Kirtex-7 series FPGA chips, the NoC prototype for LTE common baseband processing application is implemented, and the function and performance of each high-speed interface designed in this paper are tested and verified.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP393.11;TP334.7

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