一种DSP和通用CPU一体化的处理器架构及其4核实现

发布时间：2018-05-30 18:43

本文选题：多核处理器 + DSP和CPU一体化　；参考：《微电子学与计算机》2014年10期

【摘要】：提出了一种DSP和通用CPU一体化的处理器架构,并完成了一款基于该架构的同构4核处理器设计和流片验证.该处理器基于VLIW结构,支持自主定义的DSP指令系统,兼容现有通用的MIPS 4KC处理器指令集,支持最大8个指令通道的并行发射.处理器在不改变CPU的指令编码以及执行顺序的前提下,实现了芯片结构上的DSP和CPU执行处理的一体化,适合在统一的平台上同时完成宽带通信和多媒体的信号和协议处理的嵌入式应用开发.处理器内核通过自主定义的DSP指令字中前后并行标识位和一条专用的前导paralink指令实现了DSP与CPU指令的并行发射.在4核处理器的同构架构上,采用了全局读局部写的多核间片上数据存储策略,在控制硬件开销的基础上实现片上数据的共享.仿真和流片验证结果表明,所提出的DSP和CPU一体化处理器架构可行,在宽带通信和多媒体等嵌入式应用上具有优势.
[Abstract]:An integrated processor architecture of DSP and general CPU is proposed, and a isomorphic 4-core processor based on this architecture is designed and verified. The processor is based on VLIW architecture, supports the self-defined DSP instruction system, is compatible with the instruction set of the existing MIPS 4KC processor, and supports the parallel transmission of up to 8 instruction channels. Without changing the instruction encoding and execution order of CPU, the processor realizes the integration of DSP and CPU execution on chip structure. It is suitable for the embedded application development of broadband communication and multimedia signal and protocol processing simultaneously on the unified platform. The processor kernel implements the parallel transmission of DSP and CPU instructions through the parallel identifier and a special leading paralink instruction in the self-defined DSP instruction word. Based on the isomorphic architecture of the 4-core processor, a multi-core data storage strategy based on global read local write is adopted, and the data sharing is realized on the basis of controlling the hardware overhead. Simulation and chip verification results show that the proposed DSP and CPU integrated processor architecture is feasible and has advantages in embedded applications such as broadband communication and multimedia.
【作者单位】：中国科学院微电子研究所嵌入式与多核DSP实验室;
【基金】：中国科学院知识创新项目(KGCX2-YW-134)
【分类号】：TP332

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