一款同构四核芯片内核和存控加固设计与实现

发布时间：2018-05-31 05:15

本文选题：加固设计 + 流水线　；参考：《国防科学技术大学》2013年硕士论文

【摘要】：随着计算机技术和微电子技术的不断发展，航天级处理器在星载和宇航系统中得到了不断的应用。我校自主设计和实现的RAD_X处理器就是这样一款航天级同构四核芯片。设计航天级芯片时必须在电路设计时就进行特别考虑，以避免空间辐照对电路工作的不利影响。本论文针对RAD_X处理器多个核心部件的抗辐照需求，设计和实现了多种加固电路。本课题基于0.13um CMOS工艺，采用半定制的设计流程，对该处理器核心部件进行了全面的加固逻辑设计和验证。论文研究的主要内容和工作成果包括以下几个方面：初步研究与分析了空间辐射的复杂环境，并总结了影响芯片可靠性的几种辐射效应。在体系架构基础上针对SEU的影响，提出了RAD_X体系结构级的加固设计策略。针对内核整数部件流水线栈寄存器和寄存器文件的结构特点和抗辐照要求，提出了流水线栈寄存器的三模冗余加固方案以及寄存器文件的扩展汉明码加固方案，并进行了逻辑实现和可靠性验证。针对Cache系统的总体结构特点和抗辐照要求，提出了对其进行分组奇偶校验码加固设计的方案并通过数据重载更新其出错数据，并进行了逻辑实现和可靠性验证。针对主存控制器的总体结构特点和抗辐照要求，提出了对其进行BCH校验码加固设计的方案，并进行了逻辑实现和可靠性验证。经模拟仿真以及FPGA验证，本论文所做的所有加固设计功能正确。芯片的工作频率可以达到100MHz。理论分析表明，，芯片的故障率从0.4596错误/设备一天降低到2.161195e-8错误/设备-天。这些指标都已经完全达到了预定的性能。
[Abstract]:With the development of computer technology and microelectronics technology, spaceflight processors have been used in spaceborne and aerospace systems. Our own design and implementation of the RAD_X processor is such a spaceflight-level isomorphism four-core chip. In order to avoid the adverse effects of space irradiation on circuit operation, special consideration should be given to the design of spaceflight chips. In order to meet the radiation resistance requirement of several core components of RAD_X processor, a variety of reinforcement circuits are designed and implemented in this paper. Based on the 0.13um CMOS process, the core components of the processor are designed and verified by semi-custom design process. The main contents and work results of the thesis include the following aspects: The complex environment of space radiation is preliminarily studied and analyzed, and several radiation effects affecting the reliability of the chip are summarized. According to the influence of SEU, the reinforcement design strategy of RAD_X architecture level is put forward on the basis of architecture. According to the structural characteristics and irradiation-resistant requirements of pipeline stack registers and register files of kernel integers, this paper proposes a three-mode redundancy reinforcement scheme for pipeline stack registers and an extended hamming code reinforcement scheme for register files. Logic realization and reliability verification are also carried out. According to the overall structural characteristics and irradiation-resistant requirements of Cache system, a scheme of block parity check code reinforcement design is proposed, and the error data is updated by data overload, and the logic implementation and reliability verification are carried out. According to the overall structure characteristics and irradiation-resistant requirements of the main memory controller, the scheme of BCH check code reinforcement design is proposed, and the logic realization and reliability verification are carried out. Through simulation and FPGA verification, all the reinforcement design functions of this paper are correct. The working frequency of the chip can reach 100 MHz. Theoretical analysis shows that the failure rate of the chip is reduced from 0.4596 error / device per day to 2.161195e-8 error / device-day. These indicators have fully achieved the intended performance.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332;V446

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