高密度闪存信道仿真及低复杂度纠错技术研究

发布时间：2018-06-04 04:04

本文选题：NAND闪存 + 多层单元(MLC)存储技术　；参考：《广东工业大学》2017年硕士论文

【摘要】：随着电子产品的普及,人们每天在互联网与移动互联网上产生大量的数据,数据变得越来越重要,未来将进入一个数据的时代。对于这些庞大的数据,需要设备来进行存储。NAND闪存作为一种非易失存储器件已在电子产品、数据存储系统中得到了广泛的使用。为了满足大容量数据存储的需求,多层单元(MLC)存储技术的出现突破了原本单层单元(SLC)存储技术的局限。MLC存储技术通过在单个闪存单元中存储多个比特信息,提高了NAND闪存的存储密度。然而,制作工艺不断缩小NAND闪存的芯片尺寸,导致了相邻闪存单元间的干扰(CCI)变得越来越严重,成为了目前影响NAND闪存存储可靠性的主要因素。除此之外,在存储过程中还存在着其他噪声以及NAND闪存使用寿命的影响,这些干扰都会使得数据在存储及读取过程中出现错误。如何提高高密度NAND闪存的存储可靠性,已经成为了目前存储研究的热点。常用的纠错方法有通过采用合适的纠错码型和有效的译码算法,在信息写入到NAND闪存块之前进行编码操作,在信息读取之后进行译码操作,最后还原出原始信息,从而提高存储可靠性。另外,信号处理方法也是另外一个提高存储可靠性的新途径,例如对NAND闪存阈值电压信号的预处理技术和后补偿处理技术。本文主要对高密度NAND闪存信道进行了深入的分析与仿真,并在此基础上开展了低复杂度纠错技术的研究。具体工作如下:(1)结合高密度NAND闪存的结构、擦除编程原理及相邻闪存单元间干扰的特性,建立一个高密度NAND闪存信道仿真模型。在此信道模型的基础上,可以方便地进行高密度NAND闪存的纠错技术研究。通过对信道模型中的信道参数及干扰因子进行设置,可以观察纠错方法在高密度NAND闪存的性能表现,从而设计出有效的纠错方法。(2)从差错控制编码方向上,采用了在目前流行的、具有优异纠错性能的低密度奇偶校验(LDPC)码作为高密度NAND闪存的纠错码型,同时结合高密度闪存信道的特性设计了一种改进型软可靠性迭代大数逻辑译码(modified SRBI-MLGD,MSRBI-MLGD)算法,从而提高了信息存储的可靠性。该算法在保持较好纠错性能的同时,又降低了译码的复杂度。(3)从信号处理方向上,提出了一种低检测延时的后补偿(LL-Post-comp)信号处理方法。NAND闪存单元的比特信息实际是通过闪存单元的阈值电压表示的。当NAND闪存发生干扰时,闪存单元的阈值电压就会发生变化从而导致比特信息出错。该后补偿信号处理方法可以对被干扰闪存单元阈值电压进行补偿,从而提高存储的可靠性。同时在检测闪存单元的阈值电压上,只产生较低延时的开销。
[Abstract]:With the popularity of electronic products, people produce a large number of data on the Internet and mobile Internet every day, data become more and more important, the future will enter a data era. For these huge data, it is necessary to store .NAND flash memory. As a non-volatile memory device, it has been widely used in electronic products and data storage systems. In order to meet the demand of large capacity data storage, the emergence of multilayer cell (MLC) memory technology breaks through the limitation of the original single-layer unit (SLC) storage technology. MLC memory technology stores multiple bits of information in a single flash memory unit. The storage density of NAND flash memory is improved. However, the fabrication process has reduced the chip size of NAND flash memory, resulting in more and more interference between adjacent flash memory units, which has become the main factor affecting the reliability of NAND flash memory. In addition, there are other noises in the stored procedure and the influence of the NAND flash memory lifetime, which will cause errors in the data storage and reading process. How to improve the storage reliability of high density NAND flash memory has become a hot research topic. The commonly used error correction methods include coding operation before the information is written to the NAND flash block, decoding operation after reading the information, and restoring the original information by adopting the appropriate error correction code type and effective decoding algorithm. Thus, the storage reliability is improved. In addition, signal processing is another new way to improve storage reliability, such as pre-processing of NAND flash threshold voltage signal and post-compensation processing. In this paper, the high density NAND flash channel is deeply analyzed and simulated, and the low complexity error correction technology is studied. The main work is as follows: 1) combined with the structure of high density NAND flash memory, erasure programming principle and the characteristics of interference between adjacent flash memory units, a channel simulation model of high density NAND flash memory is established. On the basis of this channel model, the error correction technology of high density NAND flash memory can be conveniently studied. By setting the channel parameters and interference factors in the channel model, the performance of error correction method in high density NAND flash memory can be observed, and an effective error correction method. The low density parity check (LDPC) codes, which are popular at present and have excellent error-correcting performance, are used as error correction codes for high-density NAND flash memory. At the same time, a modified SRBI-MLGDU MSRBI-MLGDX algorithm is designed to improve the reliability of information storage by combining the characteristics of high-density flash channel. The algorithm not only maintains better error-correcting performance, but also reduces the complexity of decoding. A low detection delay post-compensated LL-Post-compp signal processing method is proposed. The bit information of NAND flash memory unit is actually expressed by the threshold voltage of the flash memory unit. When the NAND flash is interfered, the threshold voltage of the flash memory unit changes, resulting in bit error. The post-compensation signal processing method can compensate the threshold voltage of the disturbed flash memory unit, so as to improve the reliability of the memory. At the same time, the threshold voltage of the flash memory unit is detected only with lower delay overhead.
【学位授予单位】：广东工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP333;TN911.22

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