基于TMS320VC33平台的星载EDAC系统的FPGA设计与实现

发布时间：2018-06-04 05:14

本文选题：纠错检错(EDAC) + 单粒子翻转(SEU)　；参考：《国防科学技术大学》2012年硕士论文

【摘要】：由于受到空间辐射的影响，使得存储器较大概率发生单粒子翻转事件，严重影响了航天设备运行的可靠性。本文基于TMS320VC33平台自主设计实现了基于FPGA的32位EDAC系统，当存储器发生SEU事件时，该EDAC系统能够正确实现纠1检2功能，克服了SEU事件给星载计算机带来的影响。本文的主要贡献包括： (1)研究了用于EDAC纠1检2码的编解码的基本理论，对比实现了三种纠1检2码：(39,32)扩展Hamming码，(39,32)Hisao码和(40,32)SEC-DED码，从FPGA实现的逻辑延时考虑，最终选择(40,32)SEC-DED码作为32位DAC系统的码型设计基础； (2)基于TMS320VC33平台，采用Verilog HDL语言设计实现了EDAC编解码模块，采用子表达式共享技术优化了EDAC译码逻辑；并针对SEU事件设计实现了发生1-bit错时EDAC自动回写功能。综合结果表明，EDAC模块在Actel FPGAA54SX72A的最大组合逻辑延时为22.677ns。板级测试表明，当DSP工作频率为60MHz，DSP访问SRAM需要1个等待时钟周期时，EDAC模块能够正确完成纠1检2和回写功能，满足应用需求； (3)为了进一步隐藏EDAC延时，本文尝试了采用访存地址预测方案对DSP访问SRAM的地址进行预测。当DSP工作频率为40MHz时，EDAC系统可以正常工作。对于具有大量顺序访存的应用程序，，采用访存地址预测方案可降低EDAC系统平均访存延时； (4)为了确保星载EDAC系统的高可靠性，进一步对(40,32)SEC-DED码进行了可靠性验证，设计了仿真测试用例。通过对仿真测试时间进行估算，提出重点对1位错和相邻两位错的情形进行测试。
[Abstract]:Due to the influence of space radiation, single particle flip event occurs in large probability of memory, which seriously affects the reliability of spaceflight equipment operation. In this paper, a 32-bit EDAC system based on FPGA is designed and implemented based on TMS320VC33 platform. When the SEU event occurs in memory, the EDAC system can correctly realize the function of correcting 1, check and 2, which overcomes the influence of SEU event on spaceborne computer. The main contributions of this paper include: In this paper, the basic theory of coding and decoding for EDAC correction 1, check and 2 codes is studied, and three kinds of rectifying 1 and 2 codes are compared and realized. The extended Hamming codes are as follows: / 39 / 32 / Hisao code and 40 / 32 / 32 / SEC-DED code. Considering the logic delay of FPGA implementation, Finally, the SEC-DED code is chosen as the design basis of 32-bit DAC system. 2) based on TMS320VC33 platform, the EDAC codec module is designed and implemented by Verilog HDL language, the EDAC decoding logic is optimized by subexpression sharing technology, and the EDAC auto-write-back function when 1-bit error occurs is designed and implemented for SEU events. The results show that the maximum combinatorial logic delay of EDAC module in Actel FPGAA54SX72A is 22.677 ns. The results of board level test show that the DSP module can correctly complete the function of correcting 1 check 2 and write back when the SRAM needs a waiting clock cycle when the frequency of DSP is 60 MHz. In order to further hide the EDAC delay, this paper attempts to use the memory access address prediction scheme to predict the DSP access SRAM address. The DSP system can work normally when the frequency of 40MHz is 40MHz. For applications with a large number of sequential memory access, the average memory access delay in EDAC system can be reduced by using the memory access address prediction scheme. In order to ensure the high reliability of spaceborne EDAC system, the reliability verification of SEC-DED code is further carried out, and a simulation test case is designed. By estimating the time of simulation test, the emphasis is put forward to test the case of one dislocation and two adjacent dislocations.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TN791;TP333

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