亚阈值SRAM PVT波动检测与补偿设计

发布时间：2018-06-12 22:29

本文选题：低功耗设计 + SRAM　；参考：《安徽大学》2012年硕士论文

【摘要】：近年来,以智能手机和平板电脑为代表的大量移动设备的应用增长迅速,但其普遍存在发热量过大和电池续航时间短的问题,这就给嵌入式芯片的低功耗设计带来严重的挑战。由于静态随机存储器(SRAM)在系统芯片(SoC)上的容量越来越大,SRAM所占的功耗在整个芯片中的比例也在不断上升,迫切需要解决SRAM的功耗问题。传统的方法是伴随着工艺的进步,同时降低电源电压(VDD)和阈值电压(Vth)的方法来满足性能和功耗要求,但逐渐增长的亚阈值和栅漏流限制了这种降低,所以现在需要采用新的低功耗策略。降低电源电压到阈值电压以下的设计,即亚阈值设计成为了一种潜在的低功耗应用技术,且被大量设计所证实。降低电源电压会使功耗成平方下降,但其会导致性能损失,然而在许多应用场景中,例如待机状态以及某些对性能要求不高的产品中,其中包括传感器和医疗芯片等,这种性能损失是可以接受的。因此,亚阀值的SRAM设计成为了解决系统存储器能耗的一个有效措施。进入亚阈值区后,SRAM的设计面临了很大的挑战。由于亚阀值器件电流与电源电压和阂值电压成指数关系,导致亚阈值电路的延时也与VDD和Vth成指数关系,这就导致了电路的性能对工艺波动、电源电压噪声以及温度变化(PVT)的极度敏感性。例如一个小的Vth波动,特别是由于工艺的随机掺杂波动(RDF)导致的Vth波动,会带来较大的延时波动,可能使电路的功能发生错误,降低了系统的良率。本文针对亚阈值SRAM受PVT波动的影响,主要研究了亚阈值SRAM的PVT波动检测与补偿设计。主要的研究内容包括如下： (1)常规超阈值电路设计中的PVT波动影响,分析了其中采用的波动检测方法和后续的各种补偿方法： (2)亚阈值SRAM设计所遇到的挑战,重点研究了其中的关键电路,如存储单元和灵敏放大器的设计,并提出了本文的亚阈值SRAM设计： (3)针对亚阈值SRAM受PVT波动的影响,本文创新地提出了基于其读取延时波动检测和后续电源电压调节的补偿设计方法。首先,本文构造了亚阈值SRAM的一个延时关键路径电路,利用这个电路的工作状态来反映PVT波动对亚阈值SRAM读取延时的影响,然后利用延时检测电路,对位线压差建立延时进行检测,根据检测结果,通过编码电路给出不同的补偿信息,最后利用低压差线性稳压器(LDO)来实现全局的电源电压调节以补偿PVT的波动,并构成一个自适应调节系统。通过对亚阈值SRAM以及PVT波动检测和补偿电路在不同工艺角的实验发现,采用本文设计后,在较好工艺角下,PVT检测和LDO补偿电路的输出电源电压最终稳定在300mV上,即亚阈值SRAM工作在最低的电源电压下,实现超低能耗的稳定工作；而在最差SNSP (Slow NMOS Slow PMOS)工艺角下,最终电源电压稳定在375mV,也可以实现在最差工艺角下的稳定工作；另外当温度从-20-100℃之间波动时,采用本文的设计后,读取延时平均减小了64.4%,标准差仅为未采用本文设计电路的17.3%,有效地缓解了亚阈值SRAM延时受PVT波动的影响,缩短了读取周期时间；同时每周期平均能耗仅为未采用补偿电路的24.34%,而PVT电路本身带来的额外能耗仅为4.38%,提高了能耗利用率。
[Abstract]:In recent years, a large number of mobile devices, such as smartphones and tablet computers, have grown rapidly, but there is a widespread problem of excessive heating and short battery life, which poses a serious challenge to the low power design of embedded chips. The capacity of the static random memory (SRAM) on the system chip (SoC) is becoming more and more important. Large, the proportion of SRAM's power consumption in the whole chip is also rising, and it is urgent to solve the power consumption problem of SRAM. The traditional method is with the progress of the technology, while reducing the power supply voltage (VDD) and the threshold voltage (Vth) method to meet the performance and power requirements, but the increasing subthreshold and gate drain limit the reduction of this reduction. So now we need to adopt a new low power strategy.
The design of reducing the power supply voltage to the threshold voltage, that is, the subthreshold design becomes a potential low power application technology and is proved by a large number of designs. Reducing the power supply voltage will reduce the power consumption to the square, but it can cause performance loss, however, in many applications, such as standby state and some performance requirements are not high. In the product, including sensors and medical chips, this performance loss is acceptable. Therefore, the subthreshold SRAM design is an effective measure to understand the energy consumption of system memory.
After entering the subthreshold region, the design of SRAM faces great challenges. As the sub threshold device current is exponentially related to the power supply voltage and threshold voltage, the delay of the subthreshold circuit is also exponentially related to the VDD and Vth, which leads to the extreme sensitivity of the circuit performance to the process fluctuation, the power supply voltage noise and the temperature change (PVT). For example, a small Vth fluctuation, especially the Vth fluctuation caused by the random dopant fluctuation (RDF) of the process, will bring large delay fluctuation, which may make the function of the circuit error and reduce the good rate of the system. This paper mainly studies the PVT wave detection and compensation design of subthreshold SRAM for the influence of the PVT fluctuation in subthreshold SRAM. The main contents of the study include the following:
(1) the influence of PVT fluctuation in conventional super threshold circuit design, and the wave detection methods and subsequent compensation methods adopted are analyzed.
(2) the challenge of the subthreshold SRAM design, focusing on the key circuits, such as the design of the storage unit and the sensitive amplifier, and the subthreshold SRAM design in this paper.
(3) in view of the influence of PVT fluctuation on subthreshold SRAM, this paper proposes a compensation design method based on its read delay ripple detection and subsequent power supply voltage regulation.
First, a time-delay critical path circuit of subthreshold SRAM is constructed, which uses the working state of the circuit to reflect the effect of PVT fluctuation on the reading delay of the sub threshold SRAM. Then the delay detection circuit is used to detect the delay of the bit line pressure difference, and the different compensation information is given by the coding circuit according to the detection results. The low voltage differential linear regulator (LDO) is used to realize the global power supply voltage regulation to compensate for the fluctuation of PVT, and form an adaptive regulation system.
Through the experiments of subthreshold SRAM and PVT wave detection and compensation circuit in different process angles, it is found that the output voltage of PVT detection and LDO compensation circuit is finally stabilized on 300mV, that is, subthreshold SRAM works under the lowest electric source voltage to achieve the stability of ultra low energy consumption. At the worst SNSP (Slow NMOS Slow PMOS) process angle, the ultimate power supply voltage is stable at 375mV and can also achieve stable work at the worst process angle. In addition, when the temperature fluctuates from -20-100 C, the average reading delay is reduced by 64.4%, and the standard difference is only 17.3% of the design circuit. The delay of the subthreshold SRAM is affected by the fluctuation of PVT, and the reading cycle time is shortened. At the same time, the average energy consumption per cycle is only 24.34% of the compensation circuit, and the additional energy consumption of the PVT circuit itself is only 4.38%, which improves the utilization of energy consumption.
【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333;TN47

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