QCA加法器及触发器的容错设计

发布时间：2018-06-16 10:48

本文选题：量子元胞自动机 + 容错性　；参考：《合肥工业大学》2017年硕士论文

【摘要】：以CMOS器件为核心的集成电路技术一直以来遵循着摩尔定律飞速发展,随着芯片制造工艺的进步,器件的尺寸越来越小。器件尺寸的减小使得其物理基础发生根本变化,导致电路功能出现错误,出现了高功耗、高密度、复杂布线与串扰等问题,严重影响了集成电路的发展。因此广大科研工作者寻找代替传统CMOS器件的新型器件。其中,出现于20世纪90年代的量子元胞自动机(Quantum-dot CellularAutomata,QCA)是众多替代器件中的一种代表性器件。QCA提供了一种全新的编码、传递、转换二进制信息的方式。QCA电路已被广泛研究,传统电路中的诸如存储器、触发器、加法器、乘法器等已经可以实现,而且由QCA搭建的FPGA系统也有所发展。除此之外,QCA电路的稳定性以及容错特性也有科研人员在研究。QCA电路的具体物理实现依靠于电路良好的可靠性和容错性。本文致力于QCA电路的可靠性分析和容错性设计。在设计组合逻辑电路方面,利用提出的3×5模块,来优化QCA基本逻辑单元,使得它们不仅保持正确的逻辑功能,而且在缺失一个或者两个元胞的情况下能够具有良好的容错性。利用提出的基本单元来实现了加法器电路,将其与其他存在的电路进行容错性比较发现,提出的结构优化了电路的容错性。随后在时序逻辑电路方面,提出了一种改进的双边沿触发结构及其相应的JK触发器电路与D触发器,通过概率转移矩阵(Probabilistic Transfer Matrix,PTM)和缺陷研究来分析该触发结构,结果表明改进的触发结构可靠性更高,并利用模块垂直堆叠方法来优化JK触发器电路,与之前的设计相比,新结构电路的元胞数和整体面积均有所减少。经QCADesigner仿真验证,所有电路均实现正确的逻辑功能。
[Abstract]:The integrated circuit technology with CMOS devices as the core has been following the rapid development of Moore's law. With the development of chip manufacturing technology, the device size is becoming smaller and smaller. The reduction of device size causes fundamental changes in the physical basis of the device, resulting in errors in circuit functions, high power consumption, high density, complex wiring and crosstalk problems, which seriously affect the development of integrated circuits. Therefore, researchers are looking for new devices instead of traditional CMOS devices. Quantum-dot cellular automata (QCA), which appeared in the 1990s, is a representative device of many alternative devices. QCA provides a new way of encoding, transferring and converting binary information. The QCA circuit has been widely studied. Traditional circuits such as memory, flip-flop, adder, multiplier and so on have been implemented, and the FPGA system built by QCA has also been developed. In addition, the stability and fault-tolerant characteristics of QCA circuits are also studied by researchers. The physical realization of QCA circuits depends on the good reliability and fault-tolerance of the circuits. This paper is devoted to the reliability analysis and fault-tolerant design of QCA circuits. In the design of combinatorial logic circuits, the proposed 3 脳 5 modules are used to optimize QCA basic logic units so that they can not only maintain correct logic functions, but also have good fault tolerance in the absence of one or two cells. The proposed basic unit is used to realize the adder circuit. Compared with other existing circuits, it is found that the proposed structure optimizes the fault tolerance of the circuit. In the aspect of sequential logic circuit, an improved two-sided trigger structure and its corresponding JK flip-flop circuit and D-flip-flop are proposed. The trigger structure is analyzed by probabilistic transfer matrix (probabilistic transfer matrix) and defect analysis. The results show that the improved trigger structure is more reliable, and the JK flip-flop circuit is optimized by module vertical stacking method. Compared with the previous design, the cell number and the overall area of the new structure circuit are reduced. The results of QCA designer simulation show that all circuits have correct logic function.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332.2

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