DDR3内存控制器的IP核设计及FPGA验证

发布时间：2018-06-17 14:53

本文选题：DDR3 + IP核　；参考：《兰州交通大学》2012年硕士论文

【摘要】：作为计算机系统的重要组成部件,内存性能的好坏直接影响计算机系统。由于处理器的访问请求不能被内存直接识别,因此,需要内存控制器来负责完成处理器对内存的控制操作,而内存控制器决定了计算机系统所能使用的最大内存容量、存储体数目、内存类型和速度、内存颗粒的数据深度和数据宽度等重要参数。因此,内存控制器便成为影响内存性能发挥乃至计算机系统整体性能提升的关键因素之一。内存控制器的研究也成为高性能计算、嵌入式系统等领域的研究热点之一论文在研究DDR3SDRAM JEDEC规范JESD79-3E的基础上,首先对DDR3的读写机制和关键技术进行了分析,为控制器的设计提供了理论支撑,然后结合Altera公司的外部存储器解决方案,并考虑嵌入式系统的特点,对控制器的设计方案进行了论证,设计出了DDR3内存控制器IP核的整体架构,接着,采用自顶向下的模块化设计思路,将内存控制器划分为10个子模块,并使用VHDL语言对各个模块进行编程实现。在完成控制器IP核的设计后,首先使用VHDL语言编写了测试平台(Test Bench),在Quartus10.0SP1和Modelsim软件中对内存控制器IP核进行软件仿真,接着,论文还给出用户接口模块、初始化模块、指令仲裁模块等关键子模块的RTL级仿真结果,并对仿真结果分别进行了分析。最后,在Altera Stratix IV E开发板上对控制器IP核进行了FPGA验证。本论文所设计的DDR3内存控制器IP核具有以下特点： (1)支持Unbuffer ECC or Non-ECC的全系列内存模组,最高可支持容量为8GB的内存模组。 (2)具有内存模组自动识别功能,无需进行参数配置等特点,节省了用户在使用控制器IP核时需要配置参数的工作。 (3)支持最高工作频率为800MHz,内存带宽为8500Mbps。 (4)支持Altera ALTMEMPHY数字接口。 (5)该IP核适用于嵌入式系统,具有灵活性好、可移植性强等特点。
[Abstract]:As an important component of computer system, the performance of memory directly affects the computer system. Because the access request of the processor can not be recognized directly by the memory, the memory controller is required to complete the control operation of the processor to the memory, and the memory controller determines the maximum memory capacity that the computer system can use. The number of memory, the type and speed of memory, the data depth and width of memory particles are important parameters. Therefore, memory controller becomes one of the key factors that affect the performance of memory and even the whole performance of computer system. The research of memory controller has become one of the research hotspots in the field of high performance computing and embedded system. Based on the research of JESD79-3E specification of DDR3SDRAM JEDEC, this paper first analyzes the reading and writing mechanism and key technology of DDR3. This paper provides theoretical support for the design of controller, and then demonstrates the design scheme of controller combining with the external memory solution of Altera Company and considering the characteristics of embedded system. The whole architecture of DDR3 memory controller IP core is designed. Then, the memory controller is divided into 10 sub-modules by top-down modularization, and each module is programmed with VHDL. After the design of the IP core of the controller is completed, the test platform Test Benchon is written with VHDL language, and the IP core of the memory controller is simulated in Quartus 10.0SP1 and Modelsim software. Then, the user interface module and initialization module are given. The RTL simulation results of the key sub-modules such as instruction arbitration module are analyzed. Finally, the IP core of the controller is verified on the Altera Stratix IV E development board. The IP core of DDR3 memory controller designed in this paper has the following characteristics: (1) the full series of memory modules supporting unbuffer ECC or Non-ECC, and the maximum memory module with capacity of 8GB. No need for parameter configuration, etc. This saves the user the work of configuration parameters when using the IP core of the controller. 3) supports the highest working frequency of 800MHz, memory bandwidth of 8500Mbps.4) supports Altera ALTMEMPHY digital interface. 5) the IP core is suitable for embedded system. It has the characteristics of good flexibility and portability.
【学位授予单位】：兰州交通大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333.1;TN791

【参考文献】