多级STT-RAM缓存的优化策略

发布时间：2018-06-18 00:17

本文选题：多级STT-RAM + 编码　；参考：《浙江大学》2013年硕士论文

【摘要】：Cache是缓解处理器和内存速度差异的一种非常有效的方法,但是随着工艺技术及处理器技术的飞速发展,传统的以SRAM为材料的Cache受到了面积、功耗等的限制。STT-RAM是一种新型的非易失性材料,它具有密度大、静态功耗低的特点,同时,读速度接近SRAM,写速度稍慢,因此,STT-RAM非常有希望成为未来Cache的器件。但是,STT-RAM的缺点是写能耗过高和写速度过慢,因此,针对STT-RAM的研究主要是优化STT-RAM的写操作。本文根据多级STT-RAM的特性,提出了对多级STT-RAM进行动态编码以降低多级STT-RAM的写能耗。多级STT-RAM的每个存储单元都有四种阻抗状态,可以表示2比特的数据：00、01、10、11,在多级STT-RAM上写不同的阻抗状态需要的能耗不同。通过对写L2Cache数据进行统计,我们发现,在不同的时间阶段及不同的程序中,写L2Cache的四种数据的比例在不断发生变化。因此,本文认为可以根据四种数据的比例,动态地利用多级STT-RAM的四种阻抗状态表示四种实际数据,即进行动态地编码,利用写能耗较低低的阻抗状态表示写次数较多的数据。本文针对数据比例在时间上的变化特性,及不同应用程序间数据比例的差异性,分别提出了基于时间片的动态编码策略和基于应用程序的动态编码策略。基于时间片的动态编码策略将程序划分为多个时间阶段,对每个时间阶段进行动态编码,每个阶段都选择一个最优的编码方式。基于应用程序的动态编码策略在多程序共享L2Cache的条件下,根据数据块所属的应用程序进行动态编码。实验结果表明,基于时间片的动态编码策略和基于应用程序的动态编码策略分别能降低2.7%和4.5%的写能耗。本文对多处理器共享的STT-RAM Cache架构上的缓存替换策略进行了优化。通过实验发现Cache上的数据块替换时,相同应用程序数据块间的替换比不同应用程序数据块间的替换在总体上存在更多的相同数据。在写前读策略下,相同数据越多,需要进行的写操作就越少。本文对多处理器共享的缓存替换策略进行了改进,通过预测机制寻找无效数据块,在缺失率没有明显下降的前提下,增加相同应用程序数据块间的替换,以减少STT-RAM Cache上的写次数。通过实验表明,对缓存替换策略进行改进可以降低5.4%,并且系统性能有1.5%的提升。综上所述,本文通过动态编码策略和改进的Cache替换策略对基于多级STT-RAM的Cache进行了写操作的优化,实验结果表明,这些优化策略能降低多级STT-RAM Cache上的写能耗。
[Abstract]:The cache is a very effective way to alleviate the difference of processor and memory speed , but with the rapid development of process technology and processor technology , the traditional SRAM - based cache is limited by area , power consumption , etc . STT - RAM is a new type of non - volatile material . The STT - RAM is a new type of non - volatile material . The STT - RAM is very promising to be a future cache . However , STT - RAM has the disadvantage that the write power consumption is too high and the write speed is too slow . Therefore , the research on STT - RAM is mainly to optimize the write operation of STT - RAM .

In this paper , according to the characteristics of multi - stage STT - RAM , the dynamic coding of multilevel STT - RAM is proposed to reduce the write power consumption of multilevel STT - RAM . Four kinds of impedance states can be expressed in each memory cell of multi - stage STT - RAM . Four kinds of data of L2Cache can be expressed in different time periods and different programs .

The dynamic coding strategy based on time slice is divided into a plurality of time phases , the dynamic coding is carried out for each time phase , and an optimal coding mode is selected for each stage . The dynamic coding strategy based on the application program is dynamically coded according to the application program to which the data block belongs . The experimental results show that the dynamic coding strategy based on time slice and dynamic coding strategy based on application program can reduce the write power consumption of 2.7 % and 4.5 % respectively .

The cache replacement strategy on the multi - processor shared STT - RAM Cache architecture is optimized . When the data block on the Cache is replaced by the experiment , the substitution between the same application data blocks is much less than that of the different application data blocks . In the pre - write read strategy , the more the same data is needed , the less write operation is required . In this paper , the cache replacement strategy of the multi - processor sharing is improved , and the number of writes on the STT - RAM cache is reduced . The experiment shows that the improvement of the cache replacement strategy can be reduced by 5.4 % , and the performance of the system is improved by 1.5 % .

In conclusion , this paper optimizes the write operation of Cache based on multilevel STT - RAM by dynamic coding strategy and improved Cache replacement strategy , and the experimental results show that these optimization strategies can reduce write power consumption on multilevel STT - RAM Cache .
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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