模式可配置的NAND flash纠错系统设计与实现

发布时间：2018-06-24 00:11

本文选题：Nand + flash存储器　；参考：《中南大学》2013年硕士论文

【摘要】：根据NAND flash存储器的特点与性能,推导出了NAND flash存储器的纠错系统参数设计的方法。针对NAND flash存储器,设计了一种模式可配置的纠错系统的电路结构,该结构可以预防错误位数大于设计纠错位数的情况发生。在传统串行BCH编译码算法电路设计方法的基础上,导出8位并行的BCH编译码算法电路设计方法。提出了一种高速并行BCH编译码的电路设计方法,并导出一种无需有限域求逆运算的BM迭代算法的硬件实现方法。通过对求解有限域方程模块复用的方法,同时结合流水线技术与乒乓操作技术,巧妙的实现以较小的硬件逻辑资源开销获得纠错系统性能的提高。完成电路功能设计后,使用Modelsim软件对纠错系统电路进行了详细的功能仿真分析。对纠错系统电路进行了功耗估计分析,并采取了一定的优化设计方法降低电路的整体功耗。该纠错系统电路已在Altera公司的EP4CE15E22C8系列FPGA芯片上实现,并进行了测试分析,测试结果表明,在相同的系统工作频率下,该纠错系统电路的数据吞吐率是传统串行纠错电路的八倍,而硬件逻辑资源开销只增加了一倍。不同于传统的NAND flash纠错电路,该纠错电路结构相对独立,可移植性强,可满足多种应用场合的需要。图46幅,表4个,参考文献61篇。
[Abstract]:According to the characteristics and performance of NAND flash memory, the design method of error correction system parameters of NAND flash memory is deduced. For NAND flash memory, a mode configurable circuit structure of error-correcting system is designed, which can prevent the occurrence of the error bit number larger than the designed error correction bit number. Based on the traditional circuit design method of serial BCH encoding and decoding algorithm, an 8-bit parallel circuit design method for BCH encoding and decoding algorithm is derived. A high speed parallel BCH encoding and decoding circuit design method is proposed, and a hardware implementation method of BM iterative algorithm without finite field inversion is derived. By using the module reuse method to solve the finite field equations and combining the pipeline technology with the ping-pong operation technology, the performance of the error correction system can be improved with less hardware logic resource overhead. After completing the circuit function design, the function simulation analysis of error correction system circuit is carried out with Modelsim software. The power estimation analysis of error correction system circuit is carried out, and a certain optimal design method is adopted to reduce the overall power consumption of the circuit. The error correction system circuit has been implemented on EP4CE15E22C8 series FPGA chip of Altera Company, and has been tested and analyzed. The test results show that under the same operating frequency, the data throughput of this error correction system circuit is eight times that of the traditional serial error correction circuit. The cost of hardware logic resources has only doubled. Different from the traditional NAND flash error correction circuit, the structure of the circuit is relatively independent and portability, which can meet the needs of many applications. 46 figures, 4 tables, 61 references.
【学位授予单位】：中南大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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