基于FPGA的PCI Express传输设计

发布时间：2018-07-01 08:03

本文选题：PCI + Express　；参考：《重庆大学》2012年硕士论文

【摘要】：PCI Express(PCIE)总线作为第三代IO总线技术，因其具有传输带宽高、全新的点点互连架构和对PCI总线高度兼容等优点已在计算机平台中获得广泛应用。为充分发挥PCIE总线的优点，推广PCIE总线在嵌入式系统等场合的应用，本文设计了一款基于FPGA的PCIE数据传输系统，为应用PCIE进行数据传输提供了一种新的低成本方案。本文在对PCIE协议深入研究的基础上，采用自顶向下的设计思想，对PCIE数据传输系统进行顶层设计和模块划分，根据PCIE IP接口完成PCIE数据传输系统应用层的RTL级描述、仿真及验证，分析了其仿真和验证结果，，并对系统进行实际测试。论文主要包括以下几方面的内容：首先，对PCIE协议规范进行全面详细的研究，在透彻理解PCIE协议的基础上，分析PCIE纯粹端点设备的实现条件，选定系统开发平台，按照自顶向下的设计思想，对PCIE数据传输系统进行顶层设计和模块划分。其次，利用Quartus II工具对PCIE IP进行例化并分析IP接口，采用Verilog HDL对所划分的PCIE IP配置模块、PCIE应用层辅助模块、PCIE应用层核心模块进行RTL级设计。其中PCIE IP实现了PCIE协议功能，通过64位Avalon-ST接口和应用层进行数据通信；PCIE IP配置模块实现了PCIE IP配置信号采集功能和通过LMI接口配置PCIE配置空间错误报告能力寄存器功能；PCIE应用层辅助模块实现了接收端口转换、发送端口转换、接收数据缓冲和MSI缓冲功能；应用层核心模块实现了Rc_slave和链式DMA数据传输功能。论文在DMA基础上实现了链式DMA功能，减少了数据传输对CPU资源的占用，大大提高了传输效率。最后，对所设计的PCIE数据传输系统整体进行仿真测试。搭建仿真测试平台，对系统整体进行功能仿真，将综合适配后的电路下载到FPGA中进行时序验证，在PC机上利用软件对系统进行实际测试，并对相关仿真测试结果进行分析。基于FPGA的PCIE数据传输系统的仿真和测试结果表明，系统各模块逻辑功能均达到设计要求，PCIE数据传输系统可通过Rc_slave和链式DMA两种模式和PC机主存储器交换数据，DMA读速度达173MB/S，DMA写速度达207MB/S。本设计为利用低成本FPGA实现PCIE数据传输提供有效可行的实现方案，推广了PCIE总线的应用范围，具有很好的应用前景。
[Abstract]:PCI Express (PCIE) bus, as the third generation IO bus technology, has been widely used in computer platform because of its high transmission bandwidth, new point-point interconnection architecture and high compatibility with PCI bus. In order to give full play to the advantages of PCIE bus and extend the application of PCIE bus in embedded system, a PCIE data transmission system based on FPGA is designed in this paper, which provides a new low cost scheme for PCIE data transmission. Based on the deep research of PCIE protocol, the top layer design and module partition of PCIE data transmission system are carried out by adopting top-down design idea, and the RTL level description of PCIE data transmission system application layer is completed according to the PCIE IP interface. Simulation and verification, analysis of its simulation and verification results, and the actual test of the system. This paper mainly includes the following aspects: first, the PCIE protocol specification is studied in detail, on the basis of thorough understanding of the PCIE protocol, the realization conditions of PCIE pure endpoint equipment are analyzed, and the system development platform is selected. According to the idea of top-down design, the top-level design and module partition of PCIE data transmission system are carried out. Secondly, we use Quartus II tool to illustrate the PCIE IP and analyze the IP interface, and use Verilog HDL to design the PCIE application layer core module with Verilog HDL. The PCIE IP implements the PCIE protocol function. The PCIE IP configuration module realizes the PCIE IP configuration signal collection function and the PCIE configuration spatial error reporting capability register function through the 64-bit Avalon-St interface and the application layer data communication module. The PCIE application layer auxiliary module realizes the functions of receiving port conversion sending port conversion receiving data buffering and MSI buffering while the application layer core module realizes the functions of RC slave and chain DMA data transmission. On the basis of DMA, the paper realizes the chained DMA function, reduces the occupation of CPU resources by data transmission, and improves the transmission efficiency greatly. Finally, the PCIE data transmission system is simulated and tested. A simulation test platform is built to simulate the whole system. The integrated adapted circuit is downloaded to FPGA for timing verification. The software is used to test the system and the related simulation test results are analyzed. The simulation and test results of PCIE data transmission system based on FPGA show that, The logical functions of each module of the system can meet the design requirements. PCIE data transmission system can exchange data reading speed of 173 MB / Schi-DMA through two modes of RcServe and chain DMA and PC main memory with a speed of 207MB / s. This design provides an effective and feasible scheme for PCIE data transmission using low cost FPGA, and extends the application range of PCIE bus, and has a good application prospect.
【学位授予单位】：重庆大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP336

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