面向嵌入式SOC的Memory Compiler设计与实现

发布时间：2018-07-08 19:45

本文选题：编译器 + SRAM　；参考：《安徽大学》2012年硕士论文

【摘要】：存储器设计是当前数字系统设计中不可或缺的组成部分,在电子通信、消费类电子产品、个人电脑、大型电脑、卫星等领域中都有存储器的广泛应用。在SoC设计中,设计人员通常将存储器嵌入到SoC中,这种做法在提高系统效率的同时减少了电源的功耗和封装成本。SIA(Semiconductor Industry Association)的统计数据表明,集成电路技术的发展使单个芯片中能够集成更大面积的存储器,进而使存储器在整个SoC面积中占据支配地位,预计在未来几年中存储器面积的比例还会进一步加大。当前,各种类型存储器的市场占有率排序依次为DRAM、SRAM、ROM、 EPROM、E2PROM和Flash。由此可见静态随机存储器SRAM的广泛应用前景。通常的嵌入式SRAM设计有两种方式：一是全定制设计,根据要求人工完成电路、版图等的设计和拼接。全定制方法设计存储器是以存储器密度、速度、功耗、产率和封装尺寸为主要考虑因素的,其设计周期通常需要数月甚至几年的时间,而且需要大量的人力、物力投入,最终实现的是一款符合单一用户要求的存储器设计；另一种是编译器(Compiler)技术,就是采用预先设计的SRAM模块电路建立基本单元库,根据对SRAM的字长和字深的要求由编译器程序调用库文件最终完成SRAM电路、版图的拼接和实现,其电路和版图以及verilog等格式的文件由编译器自动生成,用户通过在操作界面上简单的设置就可以自己产生所需符合要求的存储器单元模块的GDSII文件和网表文件等,用户不能修改电路的内部结构和版图。在实际的应用中,不同的应用场合必然对存储器设置提出不同的要求。传统的存储器全定制实现的方法虽然能够针对应用场合进行设计并获得良好的功耗、性能面积等属性,但是这种方法同时也具有高成本和长设计周期的缺点,并不适用与大范围的推广。因此开发一款能够生成特定尺寸范围内存储器的Memory Compiler具有广泛的应用价值本文选择Memory Compiler的方法,其目的是能够根据用户的需要在保持一定的性能和功耗属性的前提下自动生成特定尺寸的存储器。在文中我们对编译器实际设计过程中的各个环节进行了洋细的介绍,对各种常见的编译器实现方法进行了深入的探讨,最终实现了一款在较大尺寸范围内(深度16-8192字、宽度2-128位)可配置的SRAM Compiler,该编译器具备高速和低功耗两种工作模式,编译产生的SRAM性能不低于相同工艺条件下相同配置SRAM的典型性能。
[Abstract]:Memory design is an indispensable part of the current digital system design. It is widely used in the fields of electronic communication, consumer electronics, personal computer, mainframe computer, satellite and so on. In SoC design, designers usually embed memory into SoC, which not only improves system efficiency, but also reduces power consumption and encapsulation cost of Sia (Semiconductor Industry Association) statistics. With the development of integrated circuit (IC) technology, a larger area of memory can be integrated into a single chip, and then memory occupies a dominant position in the whole SoC area. It is expected that the proportion of memory area will be further increased in the next few years. At present, the order of market share of various types of memory is DRAM SRAM rom, EPROMU E2PROM and Flash. It can be seen that static random access memory (SRAM) is widely used. There are two ways to design embedded SRAM: one is fully customized design, according to the requirements of manual circuit, layout design and splicing. Fully customized memory design is based on memory density, speed, power consumption, productivity and package size. Its design cycle usually takes months or even years, and requires a lot of manpower and material investment. Finally, a memory design that meets the requirements of a single user is realized, and the other is the Compiler technology, which uses the pre-designed SRAM module circuit to build the basic cell library. According to the requirements of word length and word depth of SRAM, the SRAM circuit is finally completed by the compiler program calling library file, the layout is spliced and implemented, and the circuit, layout and files in verilog format are automatically generated by the compiler. The user can produce the GDSII file and the network table file of the memory cell module by setting up on the operation interface. The user can not modify the internal structure and layout of the circuit. In practical applications, different applications must put forward different requirements for memory settings. Although the traditional fully customized memory implementation method can be designed for applications and obtain good properties such as power consumption, performance area, but this method also has the disadvantages of high cost and long design period. Do not apply to a wide range of promotion. So developing a memory Compiler that can generate memory in a given size range has a wide range of applications. This paper introduces the method of selecting memory Compiler. The purpose is to automatically generate memory of specific size according to the needs of users while maintaining certain performance and power properties. In this paper, we give a detailed introduction to the various links in the actual design of the compiler, and discuss in depth various common compiler implementation methods. Finally, we realize a large size range (depth 16-8192 words). SRAM Compiler with a width of 2-128 bits is configurable. The compiler has two working modes, high speed and low power consumption, and the SRAM performance produced by the compiler is not lower than that of the same configuration SRAM under the same process conditions.
【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333;TN47

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