存储器测试算法研究及应用实现
发布时间：2018-07-13 20:19
【摘要】：随着深亚微米等高科技技术的发展，存储器在SoC以及所有集成电路产品中所占的地位变得越来越重要。存储器芯片的容量变得越来越大，集成度也越来越高，使得存储器内部的晶体管以及其他部件越来越密集。正是由于存储器的高布线的密度、高复杂度和高工作频率这些因素，使得存储器芯片更容易发生各种各样的物理故障或者缺陷。存储器其结构的特殊性决定了该类芯片不能采用传统的直接物理检测。比较可行的办法就是对存储单元的状态进行不断的读写，然后与正确的存储单元的状态进行对比和比较，这样做就可以使得故障的物理表现形式转化为逻辑显示的形式。面对越来越多的测试需求，开发出高效的测试算法成为当下的研究热点。 本文分析了存储器中常见的静态和动态故障的故障原理，并给出了测试每种故障的March元素；对于目前最为流行的几种经典March算法，本文着重分析了能够覆盖所有简单静态故障的March SS算法的测试原理；有了以上两点作为理论基础，同时考虑到目前还没有任何一种算法能够覆盖所有的静态和动态故障，本文改进March SS算法，得到了可以覆盖所有静态和动态故障的March SD算法。该算法故障覆盖率高，测试复杂度较低，对进一步提高芯片的良品率，，降低芯片测试时间和成本有着十分重要的意义。 为了验证March SD算法的测试性能和效率，本文还给出了存储器测试仪的设计与实现，该测试仪可以适用于所有March算法的测试。整体架构采用目前较为流行的虚拟仪器设计技术，底层采用FPGA逻辑电路来实现对存储器芯片的矢量施加和结果返回，上位机界面采用LabVIEW图形化编程语言，完成算法的解析和测试矢量生成，并直观的显示整个测试过程。通过该测试系统，可以对比各种算法的测试性能和测试效率。
[Abstract]:With the development of deep submicron and other high-tech technologies, memory plays an increasingly important role in SoC and all integrated circuit products. The capacity and integration of memory chips become larger and higher, which makes the internal transistors and other components more and more dense. Because of the high density, high complexity and high working frequency of the memory, the memory chip is prone to a variety of physical failures or defects. Because of the particularity of memory structure, this kind of chip can not use traditional direct physical detection. The more feasible method is to read and write the state of the memory cell continuously, and then compare and compare with the correct state of the memory cell. In this way, the physical representation of the fault can be transformed into the form of logical display. In the face of more and more testing requirements, the development of efficient testing algorithms has become a research hotspot. In this paper, the fault principle of the common static and dynamic faults in memory is analyzed, and the March element to test each fault is given. This paper focuses on the test principle of March SS algorithm, which can cover all simple static faults, has the above two points as the theoretical basis, and considers that none of the algorithms can cover all static and dynamic faults at present. This paper improves the March SS algorithm and obtains the March SD algorithm which can cover all static and dynamic faults. The algorithm has high fault coverage and low test complexity. It is of great significance to further improve the chip quality rate and reduce the test time and cost of the chip. In order to verify the performance and efficiency of the March SD algorithm, the design and implementation of the memory tester are presented in this paper, which can be applied to all March algorithms. The whole architecture adopts the popular virtual instrument design technology, the bottom layer adopts FPGA logic circuit to implement the vector application and the result return of the memory chip, and the upper computer interface adopts LabVIEW graphical programming language. Complete the algorithm analysis and test vector generation, and visual display of the entire test process. Through the test system, the test performance and efficiency of various algorithms can be compared.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333
本文编号：2120622
[Abstract]:With the development of deep submicron and other high-tech technologies, memory plays an increasingly important role in SoC and all integrated circuit products. The capacity and integration of memory chips become larger and higher, which makes the internal transistors and other components more and more dense. Because of the high density, high complexity and high working frequency of the memory, the memory chip is prone to a variety of physical failures or defects. Because of the particularity of memory structure, this kind of chip can not use traditional direct physical detection. The more feasible method is to read and write the state of the memory cell continuously, and then compare and compare with the correct state of the memory cell. In this way, the physical representation of the fault can be transformed into the form of logical display. In the face of more and more testing requirements, the development of efficient testing algorithms has become a research hotspot. In this paper, the fault principle of the common static and dynamic faults in memory is analyzed, and the March element to test each fault is given. This paper focuses on the test principle of March SS algorithm, which can cover all simple static faults, has the above two points as the theoretical basis, and considers that none of the algorithms can cover all static and dynamic faults at present. This paper improves the March SS algorithm and obtains the March SD algorithm which can cover all static and dynamic faults. The algorithm has high fault coverage and low test complexity. It is of great significance to further improve the chip quality rate and reduce the test time and cost of the chip. In order to verify the performance and efficiency of the March SD algorithm, the design and implementation of the memory tester are presented in this paper, which can be applied to all March algorithms. The whole architecture adopts the popular virtual instrument design technology, the bottom layer adopts FPGA logic circuit to implement the vector application and the result return of the memory chip, and the upper computer interface adopts LabVIEW graphical programming language. Complete the algorithm analysis and test vector generation, and visual display of the entire test process. Through the test system, the test performance and efficiency of various algorithms can be compared.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333
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本文编号：2120622
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