粗粒度可重构处理器的结构研究与设计
发布时间：2018-07-26 15:08
【摘要】：随着嵌入式应用的不断多变、复杂化，传统的通用处理器以及专用集成电路很难满足高性能、高灵活性的需求。可重构处理器因其较高的能效比、运算资源丰富、互连形式灵活而在嵌入式设计领域受到广泛关注。 本文将算法分类为计算密集型、控制密集型、计算控制密集型，I/O密集型，数据密集型这五大类，并对当前主流的三种粗粒度和两种多粒度可重构处理器进行结构建模的基础上，分别进行了算法到可重构结构模型的映射。本文进而利用仿真结果从硬件利用率，计算时间，输入、输出带宽，数据组织形式，，数据复用等五个方面对可重构处理器的性能和算法的适应性进行分析。基于分析结论以及现有的可重构结构模型提出一种可重构阵列的设计结构，从阵列单元，互连结构，存储机制，配置机制，流水线，控制机制等方面全面介绍阵列结构。 本文对可重构阵列采用Verilog HDL语言进行硬件建模，并通过仿真，在TSMC90nm工艺下综合，时钟频率为100MHz，从算法映射结果的来看，与同类型可重构处理器的映射结果相比，在完成性能差不多的情况下，硬件利用率更高，同时为可重构处理器走向通用计算和相关的可重构架构设计提供了重要依据。
[Abstract]:With the increasing variety and complexity of embedded applications, it is difficult for traditional general-purpose processors and ASIC to meet the requirements of high performance and high flexibility. Reconfigurable processors have attracted wide attention in embedded design due to their high energy efficiency ratio, rich computing resources and flexible interconnection forms. In this paper, the algorithms are classified as computational intensive, control intensive, computational control intensive, I / O intensive and data intensive. Based on the structural modeling of three kinds of coarse-grained processors and two kinds of multi-granularity reconfigurable processors, The algorithm is mapped to the reconfigurable structure model. In this paper, the performance of the reconfigurable processor and the adaptability of the algorithm are analyzed from five aspects: hardware utilization, computing time, input, output bandwidth, data organization and data reuse. Based on the analysis results and the existing reconfigurable structure model, a design structure of reconfigurable array is proposed. The array structure is introduced from the aspects of array unit, interconnection structure, storage mechanism, configuration mechanism, pipeline, control mechanism and so on. In this paper, the Verilog HDL language is used to model the hardware of the reconfigurable array. The simulation results show that the clock frequency is 100 MHz under the TSMC90nm technology. From the point of view of the algorithm mapping results, compared with the mapping results of the same type of reconfigurable processors, In the case of similar performance, the hardware utilization is higher, and it provides an important basis for the reconfigurable processor to move towards general computing and related reconfigurable architecture design.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP368.12
本文编号：2146404
[Abstract]:With the increasing variety and complexity of embedded applications, it is difficult for traditional general-purpose processors and ASIC to meet the requirements of high performance and high flexibility. Reconfigurable processors have attracted wide attention in embedded design due to their high energy efficiency ratio, rich computing resources and flexible interconnection forms. In this paper, the algorithms are classified as computational intensive, control intensive, computational control intensive, I / O intensive and data intensive. Based on the structural modeling of three kinds of coarse-grained processors and two kinds of multi-granularity reconfigurable processors, The algorithm is mapped to the reconfigurable structure model. In this paper, the performance of the reconfigurable processor and the adaptability of the algorithm are analyzed from five aspects: hardware utilization, computing time, input, output bandwidth, data organization and data reuse. Based on the analysis results and the existing reconfigurable structure model, a design structure of reconfigurable array is proposed. The array structure is introduced from the aspects of array unit, interconnection structure, storage mechanism, configuration mechanism, pipeline, control mechanism and so on. In this paper, the Verilog HDL language is used to model the hardware of the reconfigurable array. The simulation results show that the clock frequency is 100 MHz under the TSMC90nm technology. From the point of view of the algorithm mapping results, compared with the mapping results of the same type of reconfigurable processors, In the case of similar performance, the hardware utilization is higher, and it provides an important basis for the reconfigurable processor to move towards general computing and related reconfigurable architecture design.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP368.12
【参考文献】
相关硕士学位论文 前1条
1 李明;几种多媒体处理算法在RCA上的映射[D];西北工业大学;2005年
本文编号：2146404
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