片上多核处理器二级Cache结构及资源管理技术研究
发布时间：2018-08-11 19:42
【摘要】：处理器与内存之间访问速度差距日益增大，有效组织和利用片上Cache资源以减少片外存储访问对于提升处理器性能至关重要。随着多核处理器的普及和半导体工艺的进步，芯片将集成更多的核，给二级Cache结构设计带来更大的压力和挑战。当前主流多核处理器采用基于LRU替换策略的共享或者私有二级Cache结构设计。然而，单一的共享或者私有Cache结构设计不能有效权衡容量与访问延迟。共享Cache结构能够有效利用资源，但是全局线延迟导致较慢的访问速度；私有Cache结构通过数据复制获得较快访问速度，但是容量限制导致较多的访问失效。此外，受组相联度、应用等因素的影响，LRU替换策略与理论最优替换策略之间的性能差距日趋增大。针对上述问题，本文深入研究了多核处理器中二级Cache资源的组织与管理机制，提出一种基于全局替换策略的可变相联度混合Cache结构模型，研究基于存储访问需求变化的动态容量划分与组均衡管理机制，并提供低功耗与可扩展优化。论文的创新点如下： 1.提出面向CMP的可变相联度混合Cache结构CMP-VH。CMP-VH将二级Cache划分成一种优化的私有/共享结构，Tag私有，数据部分私有部分共享。CMP-VH基于数据块的重用信息进行全局替换，并支持核间容量划分以适应不同应用存储访问需求的变化。使用Simics模拟器搭建8核片上多处理器平台，对SPLASH并行程序负载的模拟实验结果表明，在相同总容量前提下，CMP-VH结构下的平均二级Cache失效率与传统共享Cache结构接近，比传统私有Cache结构降低约23.37%。 2.提出基于数据项动态分配的容量划分技术VH-PAD。VH-PAD根据各个核的容量需求进行资源分配，包含初始化、重划分和回退三个阶段。初始化阶段赋予每个核相同数目资源；重划分阶段基于当前划分容量的饱和程度评估容量需求以指导容量划分；回退阶段基于当前占用容量判断是否撤销重划分阶段操作。VH-PAD通过控制共享数据项资源的动态分配实施核间容量调整。在Simics搭建的模拟平台上使用PARSEC基准程序进行实验，，发现在相同总容量前提下，VH-PAD机制下的平均二级Cache失效率比传统私有Cache结构降低约41.33%。 3.提出基于概率控制的容量划分技术VH-PS。VH-PS根据各个核的资源利用率进行资源分配，使用概率控制各个核对共享资源的竞争能力，从而实现核间容量划分。VH-PS提供一种性能监控机制评估各个核在增加一定容量后可以获得的失效率增益，并以此为基础赋予各个核不同等级的使用共享资源的概率。通过提升失效率增益大的核的概率等级，降低失效率增益小的核的概率等级，达到降低总失效率目的。VH-PS中的概率控制可以采用伪随机数或者PSR比例实现。在Simics搭建的模拟平台上使用PARSEC基准程序进行实验，发现在相同总容量前提下，与传统私有Cache结构相比，采用伪随机数实现的VH-PS下的平均二级Cache失效率降低约46.78%；采用PSR比例实现的VH-PS下的平均二级Cache失效率降低约43.05%。 4.提出基于Tag组饱和度的组均衡管理技术。由于CMP-VH中私有Tag阵列限制最大组相联度与最大可用容量，本文提出核内、核间两种Tag组均衡管理机制。将CMP-VH中的替换分成Tag项主导替换与Data项主导替换两类，并使用Tag项主导替换数目评估每个组的饱和程度，允许饱和度高的组使用核内或者核间相应饱和度低的组中资源。在Simics搭建的模拟平台上使用PARSEC基准程序进行实验，发现在相同总容量前提下，与基准CMP-VH结构相比，核内组均衡机制的平均二级Cache失效率降低约11.04%，核间组均衡机制的平均二级Cache失效率降低约18.94%。 5.提出异构可变相联度Cache结构HV-Way Cache及异构可变相联度混合Cache结构模型CMP-VHR。HV-Way Cache使用异构Tag阵列优化V-WayCache结构，以降低面积、功耗等开销。同时，为了适应未来众核处理器对低功耗与可扩展性的要求，使用异构Tag阵列和可重构数据阵列搭建异构可变相联度混合Cache结构模型，支持根据应用需求进行功耗优化。实验结果表明，HV-Way Cache结构能以较少的性能损失获得面积、功耗等开销的大幅降低。
[Abstract]:With the development of multi-core processors and semiconductor technology, more cores will be integrated into the chip, which will bring more pressure and choices to the design of secondary cache architecture. Current mainstream multicore processors use shared or private secondary cache architectures based on LRU replacement strategies. However, a single shared or private cache architecture cannot effectively balance capacity and access latency. In addition, the performance gap between LRU replacement strategy and theoretical optimal replacement strategy is increasing due to the influence of group association and application. In view of the above problems, this paper deeply studies the secondary cache resources in multicore processors. In this paper, we propose a hybrid Cache architecture model with variable associativity based on global replacement strategy. We study the dynamic capacity partitioning and group balancing management mechanism based on storage access requirement changes, and provide low power consumption and scalable optimization.
1. CMP-VH, a CMP-oriented variable associativity hybrid cache architecture, is proposed to divide the secondary cache into an optimized private/shared structure, which is Tag private and data partially private. Simics simulator is used to build a multi-processor platform on 8 cores. The simulation results of SPLASH parallel program load show that the average secondary cache failure rate of CMP-VH structure is close to the traditional shared cache structure under the same total capacity, which is about 23.37% lower than the traditional private cache structure.
2. The capacity partitioning technology VH-PAD.VH-PAD based on dynamic data item allocation is proposed to allocate resources according to the capacity requirements of each core, including initialization, re-partitioning and regression stages. VH-PAD implements inter-core capacity adjustment by controlling the dynamic allocation of shared data item resources. Experiments are carried out on Simics simulation platform using PARSEC benchmark program. It is found that the average under VH-PAD mechanism is the same total capacity. The failure rate of the two level Cache is about 41.33%. lower than that of the traditional private Cache structure.
3. A capacity partitioning technique based on probabilistic control, VH-PS.VH-PS, is proposed to allocate resources according to resource utilization of each core, and to control the competitiveness of shared resources by probabilistic control. VH-PS provides a performance monitoring mechanism to evaluate the failure rate of each core after increasing a certain capacity. The probability control of VH-PS can be realized by pseudo-random number or PSR ratio. The probability control of VH-PS can be implemented by Simics. The PARSEC benchmark program is used in the simulation platform. It is found that under the same total capacity, the average failure rate of secondary Cache in VH-PS with pseudo-random number is reduced by 46.78% compared with that in traditional private Cache structure, and the average failure rate of secondary Cache in VH-PS with PSR ratio is reduced by 43.05%.
4. A group balancing management technique based on group saturation is proposed. Since private Tag arrays in CMP-VH limit maximum group association and maximum available capacity, this paper proposes two Tag group balancing management mechanisms within and between cores. The saturation degree of each group is allowed for the group with high saturation to use the resources in the group with low core or inter-core saturation. The PARSEC benchmark program is used in the simulation platform built by Simics. It is found that under the same total capacity, the average secondary Cache failure rate of the intra-core group equalization mechanism is about 1.0 lower than that of the benchmark CMP-VH structure. 1.04%, the average two level Cache failure rate of the inter core group equalization mechanism is reduced by about 18.94%..
5. Heterogeneous variable-degree-of-association Cache structure HV-Way Cache and heterogeneous variable-degree-of-association hybrid Cache structure model CMP-VHR.HV-way Cache are proposed to optimize V-Way Cache structure by using heterogeneous Tag arrays in order to reduce the overhead of area and power consumption. The HV-Way Cache architecture is reconstructed to construct a heterogeneous variable-degree-of-association hybrid Cache architecture model to support power optimization according to application requirements. The experimental results show that the HV-Way Cache architecture can achieve a large reduction in area and power consumption with less performance loss.
【学位授予单位】：国防科学技术大学
【学位级别】：博士
【学位授予年份】：2012
【分类号】：TP332
本文编号：2178051
[Abstract]:With the development of multi-core processors and semiconductor technology, more cores will be integrated into the chip, which will bring more pressure and choices to the design of secondary cache architecture. Current mainstream multicore processors use shared or private secondary cache architectures based on LRU replacement strategies. However, a single shared or private cache architecture cannot effectively balance capacity and access latency. In addition, the performance gap between LRU replacement strategy and theoretical optimal replacement strategy is increasing due to the influence of group association and application. In view of the above problems, this paper deeply studies the secondary cache resources in multicore processors. In this paper, we propose a hybrid Cache architecture model with variable associativity based on global replacement strategy. We study the dynamic capacity partitioning and group balancing management mechanism based on storage access requirement changes, and provide low power consumption and scalable optimization.
1. CMP-VH, a CMP-oriented variable associativity hybrid cache architecture, is proposed to divide the secondary cache into an optimized private/shared structure, which is Tag private and data partially private. Simics simulator is used to build a multi-processor platform on 8 cores. The simulation results of SPLASH parallel program load show that the average secondary cache failure rate of CMP-VH structure is close to the traditional shared cache structure under the same total capacity, which is about 23.37% lower than the traditional private cache structure.
2. The capacity partitioning technology VH-PAD.VH-PAD based on dynamic data item allocation is proposed to allocate resources according to the capacity requirements of each core, including initialization, re-partitioning and regression stages. VH-PAD implements inter-core capacity adjustment by controlling the dynamic allocation of shared data item resources. Experiments are carried out on Simics simulation platform using PARSEC benchmark program. It is found that the average under VH-PAD mechanism is the same total capacity. The failure rate of the two level Cache is about 41.33%. lower than that of the traditional private Cache structure.
3. A capacity partitioning technique based on probabilistic control, VH-PS.VH-PS, is proposed to allocate resources according to resource utilization of each core, and to control the competitiveness of shared resources by probabilistic control. VH-PS provides a performance monitoring mechanism to evaluate the failure rate of each core after increasing a certain capacity. The probability control of VH-PS can be realized by pseudo-random number or PSR ratio. The probability control of VH-PS can be implemented by Simics. The PARSEC benchmark program is used in the simulation platform. It is found that under the same total capacity, the average failure rate of secondary Cache in VH-PS with pseudo-random number is reduced by 46.78% compared with that in traditional private Cache structure, and the average failure rate of secondary Cache in VH-PS with PSR ratio is reduced by 43.05%.
4. A group balancing management technique based on group saturation is proposed. Since private Tag arrays in CMP-VH limit maximum group association and maximum available capacity, this paper proposes two Tag group balancing management mechanisms within and between cores. The saturation degree of each group is allowed for the group with high saturation to use the resources in the group with low core or inter-core saturation. The PARSEC benchmark program is used in the simulation platform built by Simics. It is found that under the same total capacity, the average secondary Cache failure rate of the intra-core group equalization mechanism is about 1.0 lower than that of the benchmark CMP-VH structure. 1.04%, the average two level Cache failure rate of the inter core group equalization mechanism is reduced by about 18.94%..
5. Heterogeneous variable-degree-of-association Cache structure HV-Way Cache and heterogeneous variable-degree-of-association hybrid Cache structure model CMP-VHR.HV-way Cache are proposed to optimize V-Way Cache structure by using heterogeneous Tag arrays in order to reduce the overhead of area and power consumption. The HV-Way Cache architecture is reconstructed to construct a heterogeneous variable-degree-of-association hybrid Cache architecture model to support power optimization according to application requirements. The experimental results show that the HV-Way Cache architecture can achieve a large reduction in area and power consumption with less performance loss.
【学位授予单位】：国防科学技术大学
【学位级别】：博士
【学位授予年份】：2012
【分类号】：TP332
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