一种新的大容量SRAM编译器设计
发布时间：2018-08-12 10:15
【摘要】：介绍了一种大容量的SRAM编译器设计技术。根据SRAM容量和结构,提出了新的建模方案,并建立更优化的时序和功耗模型。同时,根据大容量SRAM在面积和性能上的需求,选择不同的译码器和拼接结构,采用合适的IP核进行拼接,并从结构上实现。对512kb和1 Mb的SRAM进行了流片测试,测试结果表明,该方案对于大容量的SRAM编译器设计是有效的。
[Abstract]:This paper introduces a large capacity SRAM compiler design technology. According to the capacity and structure of SRAM, a new modeling scheme is proposed, and a more optimized timing and power consumption model is established. At the same time, according to the demand of large capacity SRAM in area and performance, we choose different decoder and splicing structure, adopt suitable IP core to splice, and realize it from the structure. The test results of 512kb and 1Mb SRAM show that the proposed scheme is effective for large capacity SRAM compiler design.
【作者单位】： 中国科学技术大学工程科学学院;
【基金】：国家自然科学基金资助项目(61474001)
【分类号】：TP333;TP314
[Abstract]:This paper introduces a large capacity SRAM compiler design technology. According to the capacity and structure of SRAM, a new modeling scheme is proposed, and a more optimized timing and power consumption model is established. At the same time, according to the demand of large capacity SRAM in area and performance, we choose different decoder and splicing structure, adopt suitable IP core to splice, and realize it from the structure. The test results of 512kb and 1Mb SRAM show that the proposed scheme is effective for large capacity SRAM compiler design.
【作者单位】： 中国科学技术大学工程科学学院;
【基金】：国家自然科学基金资助项目(61474001)
【分类号】：TP333;TP314
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