基于DDR3内存模组的高速电路板设计
发布时间：2018-08-19 05:47
【摘要】：在计算机硬件电路设计中，内存芯片与主控芯片的互连设计是整个计算机系统设计的关键。系统能否稳定运行，与内存模组(简称内存，Memory Module)密不可分。计算机、手机和网络通信的快速发展是内存发展的后台推动力，尤其是在大数据，云处理等应用背景下，需要收集大量数据并进行实时处理，或者存储后再进行分析处理。内存的工作频率、工作电压及总线带宽等技术指标快速发展，目的在于提高内存的带宽及效率，满足CPU不断攀升的带宽及性能要求，避免其成为高速运算的瓶颈。论文针对DDR3内存模组的PCB高速电路设计不仅是国内外研究的热点，而且可为将来DDR4内存产品的设计奠定坚实基础。 本文首先分析了信号完整性和电源完整性基础理论，并将其运用于指导后期元器件布局、布线、拓扑结构、层叠结构、阻抗控制和电源分配。其次，对动态随机存储器(DRAM)的基本结构、工作原理、电气特性及时序进行了分析，根据设计要求确定核心器件选型，完成电路原理图设计，，借助Hspice/Hyperlynx前仿真工具分析DDR3地址/控制/命令/时钟/数据信号，信号时序及完整性良好。然后提出DDR3高速电路设计及布线规则，利用规则驱动PCB布局布线完成，后仿真验证PCB符合设计规范。最后，生产样品并完成整板测试。电源测试、读写测试、RMT测试，高速示波器SI测试结果良好，均符合JEDEC设计规范。
[Abstract]:In the design of computer hardware circuit, the interconnect design of memory chip and main control chip is the key of the whole computer system design. Whether the system can run stably is closely related to memory Module. The rapid development of computer, mobile phone and network communication is the background driving force of memory development, especially in the background of big data, cloud processing and other applications, it needs to collect a large amount of data and process it in real time, or analyze and process it after storage. The working frequency, working voltage and bus bandwidth of memory are developing rapidly. The purpose is to improve the bandwidth and efficiency of memory, to meet the increasing bandwidth and performance requirements of CPU, and to avoid the bottleneck of high speed operation. In this paper, the design of PCB high-speed circuit for DDR3 memory module is not only a hot topic at home and abroad, but also a solid foundation for the design of DDR4 memory products in the future. In this paper, the basic theory of signal integrity and power integrity is analyzed, and applied to guide the late component layout, wiring, topology, stack structure, impedance control and power allocation. Secondly, the basic structure, working principle, electrical characteristics and timing of dynamic random access memory (DRAM) are analyzed. According to the design requirements, the selection of core devices is determined, and the circuit schematic design is completed. The DDR3 address / control / command / clock / data signal is analyzed by Hspice/Hyperlynx simulation tools, and the timing and integrity of the signal are good. Then the DDR3 high-speed circuit design and routing rules are proposed. The rules are used to drive the PCB layout and routing. The post-simulation verifies that PCB conforms to the design specification. Finally, the sample is produced and the whole board test is completed. Power test, read and write test, high speed oscilloscope SI test result is good, all accord with JEDEC design standard.
【学位授予单位】：苏州大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP333.1
本文编号：2190777
[Abstract]:In the design of computer hardware circuit, the interconnect design of memory chip and main control chip is the key of the whole computer system design. Whether the system can run stably is closely related to memory Module. The rapid development of computer, mobile phone and network communication is the background driving force of memory development, especially in the background of big data, cloud processing and other applications, it needs to collect a large amount of data and process it in real time, or analyze and process it after storage. The working frequency, working voltage and bus bandwidth of memory are developing rapidly. The purpose is to improve the bandwidth and efficiency of memory, to meet the increasing bandwidth and performance requirements of CPU, and to avoid the bottleneck of high speed operation. In this paper, the design of PCB high-speed circuit for DDR3 memory module is not only a hot topic at home and abroad, but also a solid foundation for the design of DDR4 memory products in the future. In this paper, the basic theory of signal integrity and power integrity is analyzed, and applied to guide the late component layout, wiring, topology, stack structure, impedance control and power allocation. Secondly, the basic structure, working principle, electrical characteristics and timing of dynamic random access memory (DRAM) are analyzed. According to the design requirements, the selection of core devices is determined, and the circuit schematic design is completed. The DDR3 address / control / command / clock / data signal is analyzed by Hspice/Hyperlynx simulation tools, and the timing and integrity of the signal are good. Then the DDR3 high-speed circuit design and routing rules are proposed. The rules are used to drive the PCB layout and routing. The post-simulation verifies that PCB conforms to the design specification. Finally, the sample is produced and the whole board test is completed. Power test, read and write test, high speed oscilloscope SI test result is good, all accord with JEDEC design standard.
【学位授予单位】：苏州大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP333.1
【参考文献】
相关期刊论文 前2条
1 李晋文;胡军;曹跃胜;史林森;肖立权;;DDR3时序分析与设计[J];计算机科学;2012年04期
2 王继斌;;DDR3存储器前沿技术分析[J];科技信息;2009年34期
本文编号：2190777
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