基于拓扑排序和弹性信用的片上网络死锁恢复技术研究
发布时间：2018-09-13 21:39
【摘要】：近年来,传统驱动单处理器计算性能提升的技术逐步接近极限,在未来一段时间内CMP技术将做为提升处理器性能的主要手段。但随着单芯片上集成核心数量的增加，核间通信压力越来越大，如何充分利用片上资源，构建高效的片上通信网络，已成为计算机体系结构研究者们的重要探索方向。由于体系结构相似，片上网络所采用的技术多来自传统的片间网络，但片上环境的变化，导致这些技术不能简单地移植到片上，必须对其进行改进优化以适应片上平台新的物理特性和应用需求。 死锁恢复技术可以解决完全自适应路由中的死锁问题，但在片间网络中，由于硬件条件的限制，普遍存在精确检测难，解锁代价大等问题，限制了死锁恢复技术的发展。本文在对目前采取的各种解决死锁问题的策略进行了全面的分析的基础上，结合片上硬件环境的新特点，引入了精确回路定向（Accurate CycleForwarding，ACF）思想。并在此基础上提出了一种基于拓扑排序（Topology OrderDetection，TOD）的精确死锁检测机制和一种基于弹性信用（Elastic Credit Transfer，ECT）的死锁解锁机制。用极小的硬件开销实现了死锁恢复，，解决了上述问题。 本文完成了验证平台HNRsim，并对HNRsim模拟器编码针对本文提出思路的进行了优化。验证平台支持配置大小的Mesh和Torus网络拓扑结构，支持多种路由方式和通信模型，可自由修改路由方式以及通讯模式，网络中交换方式，报文长度，分片大小，注入率等关键参数均可以根据使用者的需求配置。在此平台上对新技术进行了测试。 本文基于上述验证平台，对TOD技术和ECT技术进行了时钟精度的模拟验证，并与其他相关技术在不同注入率及不同通信模式下进行了性能上和硬件开销上的比较。总体来看，在性能上相较于采用静态维序路由技术有较大提升，平均可以减少70%以上的传输延迟。而相比于传统的时间阈值检测搭配DISHA的死锁恢复技术也有明显的性能提升。此外在硬件开销方面，总体相比无死锁恢复技术的基本网络面积仅仅增加了13%，而相比DISHA技术节省了27%的面积开销。
[Abstract]:In recent years, the traditional drive single-processor computing performance improvement technology is gradually approaching the limit, in the future, CMP technology will be the main means to improve processor performance. However, with the increase of the number of integrated cores on a single chip, the pressure of inter-core communication is increasing. How to make full use of on-chip resources to build efficient on-chip communication networks has become an important research direction for computer architecture researchers. Because of the similar architecture, most of the technologies used in the on-chip network come from the traditional inter-chip network, but because of the change of the on-chip environment, these technologies can not be simply transplanted to the chip. It must be improved and optimized to meet the new physical characteristics and application requirements of the on-chip platform. Deadlock recovery technology can solve the deadlock problem in fully adaptive routing, but in the inter-chip network, due to the limitation of hardware conditions, there are many problems such as the difficulty of accurate detection and the high cost of unlocking, which limits the development of deadlock recovery technology. In this paper, based on the comprehensive analysis of various strategies adopted to solve the deadlock problem and the new characteristics of the on-chip hardware environment, the idea of precise loop orientation (Accurate CycleForwarding,ACF) is introduced. On this basis, an accurate deadlock detection mechanism based on topological ordering (Topology OrderDetection,TOD) and a deadlock unlocking mechanism based on elastic credit (Elastic Credit Transfer,ECT are proposed. The deadlock recovery is realized with minimal hardware overhead, which solves the above problem. This paper completes the verification platform HNRsim, and optimizes the coding of HNRsim simulator. The verification platform supports the configuration size of Mesh and Torus network topologies, supports various routing modes and communication models, freely modifies routing and communication modes, exchanges in networks, message length, slice size, and so on. The key parameters, such as injection rate, can be configured according to the user's requirements. The new technology is tested on this platform. Based on the above verification platform, this paper simulates the clock accuracy of TOD and ECT technologies, and compares the performance and hardware overhead with other related technologies in different injection rates and different communication modes. In general, compared with the static dimensionality routing technology, the performance can be greatly improved, and the average transmission delay can be reduced by more than 70%. Compared with the traditional time threshold detection and DISHA deadlock recovery technology also has a significant performance improvement. In addition, compared with the deadlock-free recovery technology, the basic network area is only increased by 13%, while compared with the DISHA technology, the total area cost is saved by 27%.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP303
本文编号：2241819
[Abstract]:In recent years, the traditional drive single-processor computing performance improvement technology is gradually approaching the limit, in the future, CMP technology will be the main means to improve processor performance. However, with the increase of the number of integrated cores on a single chip, the pressure of inter-core communication is increasing. How to make full use of on-chip resources to build efficient on-chip communication networks has become an important research direction for computer architecture researchers. Because of the similar architecture, most of the technologies used in the on-chip network come from the traditional inter-chip network, but because of the change of the on-chip environment, these technologies can not be simply transplanted to the chip. It must be improved and optimized to meet the new physical characteristics and application requirements of the on-chip platform. Deadlock recovery technology can solve the deadlock problem in fully adaptive routing, but in the inter-chip network, due to the limitation of hardware conditions, there are many problems such as the difficulty of accurate detection and the high cost of unlocking, which limits the development of deadlock recovery technology. In this paper, based on the comprehensive analysis of various strategies adopted to solve the deadlock problem and the new characteristics of the on-chip hardware environment, the idea of precise loop orientation (Accurate CycleForwarding,ACF) is introduced. On this basis, an accurate deadlock detection mechanism based on topological ordering (Topology OrderDetection,TOD) and a deadlock unlocking mechanism based on elastic credit (Elastic Credit Transfer,ECT are proposed. The deadlock recovery is realized with minimal hardware overhead, which solves the above problem. This paper completes the verification platform HNRsim, and optimizes the coding of HNRsim simulator. The verification platform supports the configuration size of Mesh and Torus network topologies, supports various routing modes and communication models, freely modifies routing and communication modes, exchanges in networks, message length, slice size, and so on. The key parameters, such as injection rate, can be configured according to the user's requirements. The new technology is tested on this platform. Based on the above verification platform, this paper simulates the clock accuracy of TOD and ECT technologies, and compares the performance and hardware overhead with other related technologies in different injection rates and different communication modes. In general, compared with the static dimensionality routing technology, the performance can be greatly improved, and the average transmission delay can be reduced by more than 70%. Compared with the traditional time threshold detection and DISHA deadlock recovery technology also has a significant performance improvement. In addition, compared with the deadlock-free recovery technology, the basic network area is only increased by 13%, while compared with the DISHA technology, the total area cost is saved by 27%.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP303
【参考文献】
相关期刊论文 前1条
1 罗欣武;戎蒙恬;刘文江;;片上系统中外部存储控制器的设计与优化[J];上海交通大学学报;2007年06期
本文编号：2241819
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