基于AES的安全协处理器设计与实现

发布时间：2018-10-05 14:29

【摘要】：随着嵌入式产品的迅速发展以及产品设计的越来越开放，嵌入式产品的知识产权保护日益成为产品开发者关注的焦点，同质化的硬件解决方案使得越来越多的产品开发者将其核心竞争力融入在嵌入式软件内，因此如何保护嵌入式软件安全成为了保护嵌入式产品的关键。文章首先分析了嵌入式软件的特点以及安全威胁来源，然后介绍了几种常见的嵌入式软件防护方案及其优缺点，在此基础上提出一种基于AES的安全协处理器的嵌入式软件防护机制，并对该安全协处理器进行了设计实现。基于协处理器的嵌入式软件防护机制有效解决了纯软件保护方案占用系统资源大的短板，以及其他硬件保护方案只单一提供身份认证的不足。该安全协处理器采用异构S盒的AES协处理器对主机身份进行验证以及对用户数据和程序进行加密处理，同时内置的EEPROM存储器能够对用户数据及程序进行安全存储。考虑到嵌入式系统资源有限等特点，安全处理器设计实现过程中采取多种优化结构和算法以在安全性、面积、速度和功耗之间取得良好平衡。在系统架构的基础上，对各个功能模块进行划分，按照ASIC设计的标准流程，用verilog硬件描述语言对该协处理器进行设计，然后采用Modelsim进行功能仿真，搭建FPGA平台进行硬件验证，在HuaHong NEC0.35微米工艺库下采用DesignCompiler进行综合，并用Astro对其进行后端版图设计，，最终在HuaHong NEC成功实现流片，并对流片后的芯片搭建硬件平台进行测试，测试结果表明该安全协处理器能够满足预期要求。
[Abstract]:With the rapid development of embedded products and the increasing openness of product design, intellectual property protection of embedded products has increasingly become the focus of product developers. The homogenous hardware solution makes more and more product developers integrate their core competence into embedded software, so how to protect the security of embedded software becomes the key to protect embedded products. This paper first analyzes the characteristics of embedded software and the source of security threats, then introduces several common embedded software protection schemes and their advantages and disadvantages. On this basis, an embedded software protection mechanism based on AES security coprocessor is proposed, and the security coprocessor is designed and implemented. The embedded software protection mechanism based on coprocessor effectively solves the problem that pure software protection schemes occupy large system resources and other hardware protection schemes only provide identity authentication. The security coprocessor uses the heterogeneous S-box AES coprocessor to verify the host identity and encrypt the user data and programs. Meanwhile, the built-in EEPROM memory can store the user data and programs safely. Considering the limited resources of embedded system, a variety of optimization structures and algorithms are adopted in the design and implementation of the security processor to achieve a good balance among security, area, speed and power consumption. On the basis of the system architecture, each functional module is divided into two parts. According to the standard flow of ASIC design, the coprocessor is designed with verilog hardware description language, and then Modelsim is used to simulate the function, and the FPGA platform is built for hardware verification. In the HuaHong NEC0.35 micron process library, DesignCompiler is used to synthesize, and the back-end layout is designed with Astro. Finally, the flow sheet is successfully realized in HuaHong NEC, and the chip behind the convection chip is built up to test the hardware platform. The test results show that the security coprocessor can meet the expected requirements.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP368.1

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