X-QDSP中EDMA控制器的设计与验证

发布时间：2018-10-10 19:13

【摘要】：当前，多核DSP是DSP技术发展的趋势。本课题源于自主研制的一款异构多核DSP芯片（X-QDSP）。该芯片由4个DSP核+1个RISC核组成，支持高速定浮点运算，具有EDMA、外部存储器、多通道缓冲串口和图形图像加速等多个外设。EDMA控制器作为控制多个内核与外设之间数据传输的关键部件，设计并实现满足多核DSP数据高速传输的EDMA控制器成为本文的主要研究内容。 1、深入研究了X-QDSP芯片的总体架构和性能的需求，通过对EDMA工作原理的分析，设计了满足该款DSP芯片需求的EDMA总体结构，并完成了对各个子模块的功能定义和详细设计。 2、每个DSP核分配了两个通用通道，每个通用通道由物理通道和逻辑通道组成。逻辑通道实现EDMA的启动，并支持参数连接、通道链接和参数RAM的更新。物理通道用于生成读写命令，并完成读写命令的分离，控制方式采用并行控制机制，读写访问采用流水线技术。 3、EDMA总线系统共有8套总线，采用读写总线分离的“双总线”结构。位宽128位的快速设备分配专用总线，慢速设备共享32位总线。仲裁机制采用固定优先级+令牌环轮转的策略，对来自SMC转发CPU的请求、通用通道、专用通道的请求进行仲裁。 4、对EDMA部件进行了模块级和系统级两个层次的验证。模块级着重于EDMA内部逻辑功能的实现。系统级主要验证EDMA同多个外部设备的系统关系。根据对EDMA的功能分析和覆盖率统计确保验证的完备性。经验证，该EDMA部件功能正确。在最坏条件下综合，，工作主频可达500MHz，面积1229368μm2，功耗235.8mW。
[Abstract]:At present, multi-core DSP is the development trend of DSP technology. This topic comes from a heterogeneous multi-core DSP chip (X-QDSP). The chip is composed of four DSP cores and one RISC core. It supports high speed fixed floating-point operation and has EDMA, external memory. Multi-channel buffer serial port and graphics and image acceleration, etc. EDMA controller is a key component to control data transmission between multiple cores and peripherals. The design and implementation of a EDMA controller to meet the high speed transmission of multi-core DSP data has become the main research content of this paper. 1. The overall architecture and performance requirements of X-QDSP chip are deeply studied, and the working principle of EDMA is analyzed. The overall structure of EDMA is designed to meet the requirements of the DSP chip, and the function definition and detailed design of each sub-module are completed. 2. Each DSP core allocates two common channels. Each common channel consists of physical channels and logical channels. Logical channels enable EDMA startup, and support parameter connections, channel links and parameter RAM updates. The physical channel is used to generate read / write commands, and the separation of read and write commands is completed. Parallel control mechanism is adopted in control mode, pipeline technology is used for read / write access. 3 / EDMA bus system has 8 sets of buses. The structure of "double bus" which is separated by read and write bus is adopted. The 128 bit wide fast device allocates the special bus, and the slow device shares 32 bit bus. The arbitration mechanism adopts a fixed priority token ring rotation strategy to arbitrate requests from SMC forwarding CPU, general channel, and special channel. 4. The EDMA components are verified at module level and system level. Module level focuses on the implementation of the internal logic function of EDMA. System level mainly verifies the system relationship between EDMA and multiple external devices. According to the EDMA function analysis and coverage statistics to ensure the completeness of the verification. It is proved that the function of the EDMA part is correct. Under the worst conditions, the main frequency can reach 500 MHz, the area is 1229368 渭 m ~ 2, and the power consumption is 235.8 MW.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

【参考文献】