DDR3 SDRAM控制器与PHY的设计与仿真

发布时间：2018-10-10 19:41

【摘要】：随着半导体技术的发展,如今计算机系统中的处理器与存储器的性能大幅度改善,工作频率也飞速上升。但是由于处理器与存储器的设计厂商不同,导致两者发展的不同步,处理器的性能远远超过存储器的,"存储墙"问题变得很严重,存储器的访存效率、带宽、工作频率很难满足现代处理器的需求,处理器的能力难以完全发挥出来,计算机系统的整体性能也因此受到限制。存储器控制器作为处理器与存储器之间数据传输的桥梁,因此研究一款高效的存储器控制器至关重要。本文首先对DDR3 SDRAM标准深入研究,分析了 DDR3操作的各种时序参数,讲解了页命中、页快速命中、页未命中等概念,指出了影响DDR3读写效率的因素,即寻址冲突。然后提出了通过对读写命令执行顺序调整以及不同Bank命令交叉执行的方式,提高读写效率。PHY将控制器和存储器连接起来,通过DQS硬核对输出的DQS信号延迟调整,完成写平衡操作,使用DQS硬核检测DQS信号,并将采样到的DQS信号相移90度作为DQ信号的采样时钟,完成读校准。本文对各模块使用Verilog HDL语言进行设计和仿真。
[Abstract]:With the development of semiconductor technology, the performance of processor and memory in computer system has been greatly improved. However, due to the difference between the processor and the memory design manufacturer, the development of the processor is out of sync. The performance of the processor is far greater than that of the memory. The problem of "memory wall" becomes very serious, and the memory access efficiency and bandwidth become very serious. The working frequency is difficult to meet the needs of modern processors, and the ability of processors is difficult to be fully developed, so the overall performance of computer systems is limited. Memory controller is a bridge between processor and memory, so it is very important to study an efficient memory controller. In this paper, the DDR3 SDRAM standard is deeply studied, and various timing parameters of DDR3 operation are analyzed. The concepts of page hit, page fast hit and page miss are explained, and the factors that affect the efficiency of DDR3 reading and writing, namely addressing conflict, are pointed out. Then, by adjusting the execution order of read and write commands and cross-executing different Bank commands, we improve the efficiency of reading and writing. PHY connects the controller and memory, and adjusts the delay of output DQS signals by DQS hard check. The write balance operation is completed, the DQS signal is detected by the DQS hard core, and the sampled DQS signal is shifted 90 degrees to be the sampling clock of the DQ signal, which is read and calibrated. In this paper, each module is designed and simulated by Verilog HDL language.
【学位授予单位】：山东大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP333

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