网络处理器中异步访问DRAM存储控制系统的设计与优化

发布时间：2018-10-16 09:15

【摘要】：随着通信技术以及微电子产业的不断发展，网络应用也在不断更新。网络带宽的急剧增长和网络协议的不断更新，使得传统的网络设备方案已经不能满足用户对于高性能和可编程方面的需求。传统的网络设备像通用处理器（GPP）虽然灵活性好、成本低，但由于它性能低下，所以不适合处理高速网络流量；ASIC（ApplicationSpecificIntegratedCircuit）虽然性能高，采用硬件的方式能够实现各种成熟的网络功能，，但由于它的设计周期长，灵活性较差，而且费用高；FPGA(FieldProgrammableGateArray)虽然可反复编程，能在一定程度上灵活的扩展业务类型，但由于受技术限制还不成熟。而ASIP（ApplicationSpecificInstructionProcessor）也就是网络处理器（NP）结合了上述传统设备的优点，由若干微处理器和一些硬件协处理器组成，并行工作，通过软件来控制处理流程。它具有可编程可扩展的特性，实现了业务灵活性与高性能的有效结合。本文中所设计的DRAM存储控制器，采用多种优化策略，以便充分提升网络处理器的其他主设备对存储器的访问效率。由于XDNP采用异构多核硬件多线程的设计结构，所以它的多个包处理引擎（PE）以及每个包处理引擎的多个线程需要不断的对片外的DRAM存储器进行访问。由于同一时刻只能有一个包处理引擎的一个线程对DRAM芯片进行访问，所以对DRAM芯片的访问延时就成了决定网络处理器性能的最关键的因素。本文所设计的DRAM存储控制器针对XDNP多核共享的访存特性，采用一种流水线结构来实现对不同部件对DRAM芯片的访存指令的处理，大大提升了DRAM控制器的访存效率以及运行频率，使得DRAM控制器的吞吐率提升了3.6倍，平均延时下降了50%。运行频率从200M提升到220M，提高了1.1倍。此外设计中还对不同设备发出的访存指令的仲裁进行了优化，采用基于Round-Robin的混合优先级的仲裁策略动态调整各类访存指令的优先级，极大的提高了DRAM控制器的效率。
[Abstract]:With the continuous development of communication technology and microelectronics industry, network applications are constantly updated. With the rapid growth of network bandwidth and the continuous updating of network protocols, the traditional network equipment solutions can no longer meet the needs of users in terms of high performance and programmable. Although traditional network devices such as (GPP) have good flexibility and low cost, but because of its low performance, it is not suitable for processing high-speed network traffic; ASIC (ApplicationSpecificIntegratedCircuit). Although the performance of; ASIC (ApplicationSpecificIntegratedCircuit) is high, it can realize all kinds of mature network functions by hardware. However, because of its long design cycle, low flexibility and high cost; FPGA (FieldProgrammableGateArray), although it can be programmed repeatedly, it can extend the service type flexibly to some extent, but it is not mature because of the technical limitation. ASIP (ApplicationSpecificInstructionProcessor), which is the network processor (NP), combines the advantages of the traditional devices mentioned above. It is composed of several microprocessors and some hardware coprocessors. It works in parallel and controls the processing flow through software. It has the characteristic of programmable and extensible, and realizes the effective combination of business flexibility and high performance. The DRAM storage controller designed in this paper adopts various optimization strategies in order to fully improve the memory access efficiency of other main devices of the network processor. Because XDNP adopts the design structure of heterogeneous multi-core hardware multithreading, its multiple packet processing engine (PE) and multiple threads of each packet processing engine need to continuously access the off-chip DRAM memory. Since only one thread of one packet processing engine can access the DRAM chip at any one time, the delay of access to the DRAM chip becomes the most critical factor that determines the performance of the network processor. The DRAM memory controller designed in this paper aims at the memory access characteristics of XDNP multi-core sharing, and adopts a pipeline structure to process the memory access instructions of different components to the DRAM chip, which greatly improves the memory access efficiency and the running frequency of the DRAM controller. The throughput of the DRAM controller is increased by 3. 6 times, and the average delay is reduced by 50 times. The operating frequency increased 1.1 times from 200m to 220m. In addition, the arbitration of memory access instructions issued by different devices is optimized. The arbitration strategy based on mixed priority of Round-Robin is used to dynamically adjust the priority of all kinds of memory access instructions, which greatly improves the efficiency of DRAM controller.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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