基于IEEE1149.6的PCIE边界扫描设计与实现
发布时间：2018-10-16 10:35
【摘要】：边界扫描技术是一种标准的数字系统测试及可测性设计方法，它在工业界得到了广泛的应用。但是随着电子技术和高速数字通信技术的飞速发展，为了提高信号的传输速率，高速接口的使用越来越广泛。第一部边界扫描技术标准为IEEEStd1149.1，它主要是针对芯片内部互连和芯片与PCB板之间的低速数字信号的测试，但是对高级数字网络中交流耦合差分信号的测试，，则表现出明显的不足。从而导致测试覆盖率大大的降低。在这种情况下，2003年IEEE通过了IEEE Std1149.6标准，这一标准主要是解决1149.1中无法检测的故障。虽然1149.6标准早在2001年就已经形成，但是由于标准需要向下兼容和处理交流特性的信号等特点，使得电路实现起来非常的困难，到目前为止，只有几款芯片真正实现这一技术。 本文主要对边界扫描技术和具有交流耦合差分特性的信号进行了理论分析和研究，针对PCIE高速接口芯片实现边界扫描设计。 1、详细分析了IEEE1149.6标准中针对交流耦合差分信号的边界扫描设计方法，提出了针对高速接口PCIE芯片的边界扫描设计方案并进行了电路逻辑设计，主要包括数字驱动器模块、数字接收器模块、模拟测试接收器模块和1149.6测试访问端口TAP。 2、采用全定制的方法实现了边界扫描电路中的数字驱动器模块和数字接收器模块的版图设计。 本文还分别对边界扫描设计电路中的指令集、交流测试信号和模块的版图设计进行了模拟验证。模拟结果表明，该边界扫描设计是正确的。
[Abstract]:Boundary scan technology is a standard method of digital system testing and testability design. It has been widely used in industry. However, with the rapid development of electronic technology and high-speed digital communication technology, in order to improve the signal transmission rate, high-speed interface is more and more widely used. The first boundary scan standard is IEEEStd1149.1, which is mainly used to test the low speed digital signal between the chip and the PCB board. However, the test of the AC coupled differential signal in the advanced digital network is obviously inadequate. This results in a significant reduction in test coverage. In this case, IEEE adopted the IEEE Std1149.6 standard in 2003, which mainly addresses undetectable faults in 1149.1. Although the 1149.6 standard was formed as early as 2001, it is very difficult to realize the circuit because the standard needs to be compatible down and the signal of AC characteristic is processed. So far, only a few chips have realized this technology. In this paper, the boundary scan technique and the signal with AC coupling difference characteristics are analyzed and studied theoretically. The design of boundary scan for PCIE high-speed interface chip is introduced. 1. The design method of boundary scan for AC coupled differential signal in IEEE1149.6 standard is analyzed in detail. The design scheme of boundary scan for PCIE chip with high speed interface is put forward and the circuit logic design is carried out, which includes digital driver module and digital receiver module. Simulation test receiver module and 1149.6 test access port TAP. 2 are used to realize the layout design of digital driver module and digital receiver module in the boundary scan circuit. The instruction set, AC test signal and layout design of the circuit are simulated and verified in this paper. The simulation results show that the boundary scan design is correct.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7
[Abstract]:Boundary scan technology is a standard method of digital system testing and testability design. It has been widely used in industry. However, with the rapid development of electronic technology and high-speed digital communication technology, in order to improve the signal transmission rate, high-speed interface is more and more widely used. The first boundary scan standard is IEEEStd1149.1, which is mainly used to test the low speed digital signal between the chip and the PCB board. However, the test of the AC coupled differential signal in the advanced digital network is obviously inadequate. This results in a significant reduction in test coverage. In this case, IEEE adopted the IEEE Std1149.6 standard in 2003, which mainly addresses undetectable faults in 1149.1. Although the 1149.6 standard was formed as early as 2001, it is very difficult to realize the circuit because the standard needs to be compatible down and the signal of AC characteristic is processed. So far, only a few chips have realized this technology. In this paper, the boundary scan technique and the signal with AC coupling difference characteristics are analyzed and studied theoretically. The design of boundary scan for PCIE high-speed interface chip is introduced. 1. The design method of boundary scan for AC coupled differential signal in IEEE1149.6 standard is analyzed in detail. The design scheme of boundary scan for PCIE chip with high speed interface is put forward and the circuit logic design is carried out, which includes digital driver module and digital receiver module. Simulation test receiver module and 1149.6 test access port TAP. 2 are used to realize the layout design of digital driver module and digital receiver module in the boundary scan circuit. The instruction set, AC test signal and layout design of the circuit are simulated and verified in this paper. The simulation results show that the boundary scan design is correct.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7
【共引文献】
相关期刊论文 前1条
1 周杰;周绍磊;彭贤;雷鸣;;边界扫描技术在板级可测性设计中的应用[J];中国测试技术;2007年04期
相关硕士学位论文 前10条
1 王哲;IRFPA读出电路设计测试及可测性设计研究[D];北京交通大学;2010年
2 代桃;多板卡电子系统的可测性设计与实现[D];电子科技大学;2011年
3 杨
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