低延时寄存器定制设计与实现
发布时间：2018-10-17 13:44
【摘要】：集成电路目前仍在按照摩尔定律飞速发展着，单一芯片晶体管数目已达到数十亿、芯片主频达到数G赫兹。目前主流芯片设计实现方法为基于标准单元库的半定制设计方法，在追求强大的可靠性和通用性时会牺牲部分性能。因此，在设计高性能处理器时，标准单元库通常难以满足速度需求。40nm工艺下普通低阈值寄存器延时大约60ps左右，对2GHz以上微处理器来说，寄存器延时已超过栈间延时的12%以上，减小寄存器延时成为提升微处理器性能的关键问题。 本文提出并实现了一类低延时脉冲寄存器（LDPR，Low Delay Pulse Register），该寄存器使用脉冲锁存器结构，节约了一级锁存延时，，在全定制精细调整结构与晶体管尺寸的情况下，大大缩短了寄存器的传播延时。同时，本文完成了LDPR寄存器成组和多种驱动能力设计以及版图绘制。版图模拟结果表明，本文设计并实现的低延时脉冲寄存器的传播延时比标准单元库中的主从边沿触发器减少50%。成组寄存器的组内寄存器时钟偏差小于0.3ps。 经过特征化的寄存器可以被主流布局布线工具识别使用，将本文提出的低延时脉冲寄存器在物理设计实例中进行可用性实验，针对实际工程问题编写了脚本，可以让工具正确的使用此类低延时寄存器。寄存器在整个物理设计流程中应用正常，未出现任何错误，实验证明本文提出的LDPR寄存器具有实用价值。
[Abstract]:The integrated circuits are still developing rapidly according to Moore's law. The number of single chip transistors has reached billions and the main frequency of chips has reached the number of G hertz. At present, the main chip design method is based on standard cell library semi-custom design method, which will sacrifice some performance while pursuing strong reliability and versatility. Therefore, when designing high performance processor, the standard cell library is difficult to meet the requirement of speed. In 40nm process, the delay of low threshold register is about 60ps, for microprocessor above 2GHz, the delay of register is more than 12% of the delay between stacks. Reducing register delay is a key problem to improve microprocessor performance. In this paper, a class of low delay pulse registers (LDPR,Low Delay Pulse Register),) is proposed and implemented, which uses pulse latch structure, saves the first stage latch delay, and adjusts the structure and transistor size with full customization. The delay of register propagation is greatly reduced. At the same time, this paper completes the LDPR register group and various driving ability design and layout drawing. The layout simulation results show that the propagation delay of the low delay pulse register designed and implemented in this paper is 50% less than that of the master-slave edge flip-flop in the standard cell library. The clock deviation of the group registers is less than 0.3 ps. The characteristic register can be recognized and used by the mainstream layout and routing tool. The low delay pulse register proposed in this paper is tested in the physical design example, and the script is written in view of the actual engineering problem. This low-delay register can be used correctly by the tool. The register is applied normally in the whole physical design process without any errors. The experiment proves that the LDPR register proposed in this paper has practical value.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332
本文编号：2276842
[Abstract]:The integrated circuits are still developing rapidly according to Moore's law. The number of single chip transistors has reached billions and the main frequency of chips has reached the number of G hertz. At present, the main chip design method is based on standard cell library semi-custom design method, which will sacrifice some performance while pursuing strong reliability and versatility. Therefore, when designing high performance processor, the standard cell library is difficult to meet the requirement of speed. In 40nm process, the delay of low threshold register is about 60ps, for microprocessor above 2GHz, the delay of register is more than 12% of the delay between stacks. Reducing register delay is a key problem to improve microprocessor performance. In this paper, a class of low delay pulse registers (LDPR,Low Delay Pulse Register),) is proposed and implemented, which uses pulse latch structure, saves the first stage latch delay, and adjusts the structure and transistor size with full customization. The delay of register propagation is greatly reduced. At the same time, this paper completes the LDPR register group and various driving ability design and layout drawing. The layout simulation results show that the propagation delay of the low delay pulse register designed and implemented in this paper is 50% less than that of the master-slave edge flip-flop in the standard cell library. The clock deviation of the group registers is less than 0.3 ps. The characteristic register can be recognized and used by the mainstream layout and routing tool. The low delay pulse register proposed in this paper is tested in the physical design example, and the script is written in view of the actual engineering problem. This low-delay register can be used correctly by the tool. The register is applied normally in the whole physical design process without any errors. The experiment proves that the LDPR register proposed in this paper has practical value.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332
【参考文献】
相关博士学位论文 前1条
1 李振涛;高性能DSP关键电路及EDA技术研究[D];国防科学技术大学;2007年
本文编号：2276842
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