访存踪迹收集工具的逻辑设计与实现

发布时间：2018-10-17 13:50

【摘要】：近些年来,内存性能的提升已成为整个计算机系统性能提升的瓶颈,而在内存系统结构的研究中,如何快速获取大量详细的系统访存踪迹信息成为对大数据应用行为分析研究的关键。况且,由于DDR内存总线上的数据速率的不断提升,现有的部分访存踪迹收集工具已经无法满足其对于准确获取较高数据速率下高访存带宽应用的访存踪迹收集需要。因此,在本文中主要针对现有的HMTT v3访存踪迹收集平台的FPGA内部逻辑进行了重新设计和优化,以满足当前访存踪迹采集的需求。作者完成的主要工作如下：(1)将HMTT v3访存踪迹收集平台能够支持的DDR3总线速率从DDR3-800提升至DDR3-1600；(2)使HMTT v3访存踪迹收集平台能够同时处理四路DDR3总线上发送来的DDR3命令、地址以及控制信息,并输出对应的系统访存踪迹信息；(3)通过采用两种不同的访存踪迹包的格式,在对访存踪迹包进行压缩的同时,完整地保留下包括完整访存时间间隔的访存踪迹信息；(4)针对访存踪迹包在传输及存储上的需求,研究并实现了在PCIe传输通道下将访存踪迹信息准确且不丢失地传输到接收机端上去的功能；(5)为现有的HMTT v3平台实现了多内存环境下的应用扩展,并实现了在同一内存通道内同时获取两个内存插槽上的系统访存行为的功能。本文所完成的工作实现了在HMTT v3访存踪迹收集平台的环境下,成功获取DDR3-1600速率下的系统访存踪迹,并将获取到的系统访存踪迹准确无误地传输到接收机端进行存储的功能。目前,本文完成的工作已经用于多个大数据应用的访存踪迹收集,为大数据访存行为的分析提供了强有力的支持,其分析的结果已经开始用于新的内存系统结构的设计与优化。
[Abstract]:In recent years, the improvement of memory performance has become the bottleneck of improving the performance of the whole computer system. How to quickly obtain a large number of detailed systematic information is the key to the analysis of big data's application behavior. Moreover, due to the continuous improvement of the data rate on the DDR memory bus, the existing part of the access and trace collection tools can no longer meet the need for accurate access and trace collection of high access bandwidth applications at higher data rates. Therefore, this paper redesigns and optimizes the FPGA internal logic of the existing HMTT v3 access and trace collection platform to meet the needs of current access and trace collection. The main works of the author are as follows: (1) the rate of DDR3 bus supported by HMTT v3 can be increased from DDR3-800 to DDR3-1600; (2) HMTT v3 can process DDR3 commands sent from four DDR3 bus at the same time. Address and control information, and output the corresponding system access and trace information; (3) by adopting two different formats of track access packet, while compressing the packet, (4) for the transmission and storage requirements of the access packet, This paper studies and realizes the function of transferring the track information to the receiver accurately and without losing in the PCIe transmission channel. (5) it implements the application extension in the multi-memory environment for the existing HMTT v3 platform. The memory access behavior of two memory slots is obtained simultaneously in the same memory channel. In the environment of HMTT v3 access and trace collection platform, this paper has successfully acquired the system access and trace under the DDR3-1600 rate, and transferred the acquired system to the receiver accurately for storage. At present, the work done in this paper has been used to collect the trace of several big data applications, which provides a powerful support for the analysis of big data's memory access behavior. The results of the analysis have been applied to the design and optimization of the new memory system structure.
【学位授予单位】：中国科学院大学(工程管理与信息技术学院)
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TP333.1

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