一个应用混合基算法的余数系统后置转换电路设计
发布时间：2018-10-18 16:59
【摘要】：针对传统的混合基算法在实现余数系统到二进制系统转换过程中的并行性问题,应用改进的混合基算法,研究与设计了一个基于模集合{2n,2n-1,2n+1-1,2n-1-1}的后置转换电路.模2n-1形式的模加法器采用相对简单的实现结构,使设计的电路避免了只读存储器及时序电路的引入,整个后置转换电路完全由简单组合逻辑及加法器级联实现,缩短了关键路径延时,减小了功率消耗,与已有的相同动态范围余数系统后置转换电路相比,性能优势明显.
[Abstract]:Aiming at the parallelism of the traditional hybrid basis algorithm in the process of realizing the conversion of residue system to binary system, a post-conversion circuit based on the modular set {2nn2n-1n-1 + 2n 1-1n + 2n-1-1} is studied and designed by using the improved hybrid basis algorithm. The modular adder in the form of modular 2n-1 adopts a relatively simple implementation structure, which avoids the introduction of read-only memory and sequential circuits, and the whole post-conversion circuit is completely realized by simple combinatorial logic and adder cascading. The critical path delay is shortened and the power consumption is reduced. Compared with the existing post-conversion circuit in the same dynamic range, the performance of the system has obvious advantages.
【作者单位】： 华南理工大学电子与信息学院;
【基金】：国家自然科学基金项目(61274085) 华南理工大学中央高校基本科研学生项目(10561201435)
【分类号】：O156;TP332.2
本文编号：2279769
[Abstract]:Aiming at the parallelism of the traditional hybrid basis algorithm in the process of realizing the conversion of residue system to binary system, a post-conversion circuit based on the modular set {2nn2n-1n-1 + 2n 1-1n + 2n-1-1} is studied and designed by using the improved hybrid basis algorithm. The modular adder in the form of modular 2n-1 adopts a relatively simple implementation structure, which avoids the introduction of read-only memory and sequential circuits, and the whole post-conversion circuit is completely realized by simple combinatorial logic and adder cascading. The critical path delay is shortened and the power consumption is reduced. Compared with the existing post-conversion circuit in the same dynamic range, the performance of the system has obvious advantages.
【作者单位】： 华南理工大学电子与信息学院;
【基金】：国家自然科学基金项目(61274085) 华南理工大学中央高校基本科研学生项目(10561201435)
【分类号】：O156;TP332.2
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1 刘建根;冗余余数系统在高斯噪声下的纠错[D];兰州大学;2012年
2 牛旭;高斯噪声下的余数系统[D];兰州大学;2012年
，本文编号：2279769
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