一种应用于DC-OFDM系统的FFT处理器设计

发布时间：2018-10-18 17:35

【摘要】：设计了一种应用于双载波正交频分复用(DC-OFDM)无线通信系统的高速、低功耗快速傅里叶变换(FFT)处理器.为降低传统并行架构带来的硬件实现开销,提出了一种新型的结合FFT分解的多路并行架构,有效减少了实现所需的乘法器和加法器数目,在提高处理器数据吞吐率的同时,进行了芯片面积的优化.另外,采用提出的处理单元实现不同的基运算,并对基-2、基-22、基-23、基-24不同架构下的定点FFT运算所需的硬件开销进行定量分析,以选择最优的基结构.最后,介绍了旋转因子乘法器的设计.设计实现的128点FFT处理器采用SMIC 0.13μm CMOS工艺,芯片面积为1.44 mm2,最大数据吞吐率达到1GS/s,在典型工作频率500MS/s下的功耗为39.5mW.与现有其他128点FFT处理器相比,减小了面积,节约了功耗.
[Abstract]:A high speed, low power fast Fourier transform (FFT) processor for dual-carrier orthogonal frequency division multiplexing (DC-OFDM) wireless communication systems is designed. In order to reduce the hardware implementation overhead brought by traditional parallel architecture, a new multi-channel parallel architecture combined with FFT decomposition is proposed, which can effectively reduce the number of multiplier and adder needed for implementation, and improve the throughput of processor data at the same time. The chip area is optimized. In addition, the proposed processing unit is used to implement different base operations, and the hardware overhead required for fixed-point FFT operations under different base-2, base-22, base-22 and base-24 architectures is quantitatively analyzed in order to select the optimal base structure. Finally, the design of rotation factor multiplier is introduced. The 128-point FFT processor is designed and implemented using SMIC 0.13 渭 m CMOS technology. The maximum data throughput of 1.44 mm2, is 1 GS / s, and the power consumption is 39.5 MW at typical operating frequency 500MS/s. Compared with other 128-point FFT processors, the area is reduced and the power consumption is saved.
【作者单位】：复旦大学专用集成电路与系统国家重点实验室;
【基金】：国家科技重大专项(2011ZX03004-001-02)资助项目
【分类号】：TP332

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