基于路访问轨迹和路休眠的高速缓存低功耗研究
发布时间：2018-11-02 20:03
【摘要】：随着集成电路工艺进入深亚微米和超深亚微米阶段,芯片的集成度不断增加,时钟频率不断提高,芯片的整体性能也随之提升。但由于单位面积上集成的晶体管数量的持续增加,芯片的功耗也不断的攀升。随着便携式移动嵌入式系统应用的不断发展和普及,低功耗的高性能嵌入式处理器已成为今后移动计算必然的发展趋势和发展要求,而其中高速缓存单元的功耗尤为突出。本文围绕嵌入式处理器的高速缓存低功耗技术,重点研究了基于路访问轨迹的低功耗指令高速缓存策略和基于路休眠的低功耗数据高速缓存策略。 针对指令高速缓存的连续访问特性提出一种基于路访问轨迹的组相联指令高速缓存的低功耗策略。该策略利用改进的指令高速缓存和转移目标缓存建立和维护运行时指令高速缓存的路访问轨迹来减少指令高速缓存命中检测及无关路访问。进一步提出了基于跨行访问前驱指针、转移前驱状态、转移前驱指针及转移目标索引的路访问轨迹信息维护策略用以降低信息重建的频度,从而更有效地利用已建立的路访问轨迹信息。实验结果表明,采用优化后的路访问轨迹策略的指令高速缓存的标志存储器访问和数据存储器访问在理想情况下分别降低到传统指令高速缓存的0.74%和25.55%。 针对数据高速缓存缓存的离散访问特性提出一种基于路休眠的数据高速缓存低功耗策略。该策略利用门控电源技术控制数据高速缓存行的通断,消除长期闲置的数据高速缓存行的静态功耗。同时进一步研究了适用于不同应用的闲置阈值,并进一步提出全局可配的闲置阈值寄存器以适应不同应用对于闲置阈值的不同要求。实验结果表明,最优情况数据高速缓存行的静态功耗可以降低到9.13%,最差情况可以降低到34.7%。
[Abstract]:With the IC process entering deep submicron and ultra-deep submicron phase, the integration level of the chip is increasing, the clock frequency is increasing, and the overall performance of the chip is also improved. But as the number of transistors integrated per unit area continues to increase, the power consumption of chips is rising. With the continuous development and popularization of portable mobile embedded system applications, low power high performance embedded processors have become the inevitable trend and development requirements of mobile computing in the future, and the power consumption of cache cells is particularly prominent. This paper focuses on the low-power cache strategy based on path access trajectory and low-power data cache strategy based on path sleep. Aiming at the continuous access characteristics of instruction cache, a low power policy of group associated instruction cache based on path access trajectory is proposed. This strategy uses improved instruction cache and transfer target cache to establish and maintain path access trajectory of runtime instruction cache to reduce instruction cache hit detection and irrelevant access. Furthermore, a path access path information maintenance strategy based on cross row access precursor pointer, transfer precursor state, transfer precursor pointer and transfer target index is proposed to reduce the frequency of information reconstruction. Thus, the established path access path information can be used more effectively. The experimental results show that the flag memory access and data memory access of instruction cache using the optimized path access path strategy are reduced to 0.74% and 25.55% of the traditional instruction cache respectively under ideal conditions. According to the discrete access characteristics of data cache, a low power policy for data cache based on path sleep is proposed. The strategy uses the gated power supply technology to control the on-off of the data cache row, and eliminates the static power consumption of the long-idle data cache row. At the same time, the idle threshold for different applications is further studied, and a globally configurable idle threshold register is proposed to meet the different requirements of different applications for idle threshold. The experimental results show that the static power consumption of the optimal data cache row can be reduced to 9.13 and the worst case can be reduced to 34.7.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333
本文编号：2306817
[Abstract]:With the IC process entering deep submicron and ultra-deep submicron phase, the integration level of the chip is increasing, the clock frequency is increasing, and the overall performance of the chip is also improved. But as the number of transistors integrated per unit area continues to increase, the power consumption of chips is rising. With the continuous development and popularization of portable mobile embedded system applications, low power high performance embedded processors have become the inevitable trend and development requirements of mobile computing in the future, and the power consumption of cache cells is particularly prominent. This paper focuses on the low-power cache strategy based on path access trajectory and low-power data cache strategy based on path sleep. Aiming at the continuous access characteristics of instruction cache, a low power policy of group associated instruction cache based on path access trajectory is proposed. This strategy uses improved instruction cache and transfer target cache to establish and maintain path access trajectory of runtime instruction cache to reduce instruction cache hit detection and irrelevant access. Furthermore, a path access path information maintenance strategy based on cross row access precursor pointer, transfer precursor state, transfer precursor pointer and transfer target index is proposed to reduce the frequency of information reconstruction. Thus, the established path access path information can be used more effectively. The experimental results show that the flag memory access and data memory access of instruction cache using the optimized path access path strategy are reduced to 0.74% and 25.55% of the traditional instruction cache respectively under ideal conditions. According to the discrete access characteristics of data cache, a low power policy for data cache based on path sleep is proposed. The strategy uses the gated power supply technology to control the on-off of the data cache row, and eliminates the static power consumption of the long-idle data cache row. At the same time, the idle threshold for different applications is further studied, and a globally configurable idle threshold register is proposed to meet the different requirements of different applications for idle threshold. The experimental results show that the static power consumption of the optimal data cache row can be reduced to 9.13 and the worst case can be reduced to 34.7.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333
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