基于IP包处理的多线程流水线处理器ASIC设计与实现
发布时间：2018-11-24 12:03
【摘要】：网络用户和数据流量的指数级增长，要求网络处理的带宽更宽、速度更快。网络处理器作为一种基于可编程的ASIC处理器，它可为系统提供类似ASIC的高性能处理速度，而且可以提供类似通用处理器的灵活性。因此满足很多应用的性能要求。 作为网络处理器中的核心设计单元，多线程流水线处理器的任务就是完成对所有经过网络处理器的数据包校验和验证，包头处理和分类，，表查找和转发，包在存储单元的存储，包头修改，包往正确端口的转发等。因此，多线程流水线处理器设计的好坏很大程度上决定了网络处理器的性能，多线程流水线处理器的频率高低直接影响整个设计平台的工作频率，吞吐量以及整体性能。 本文主要完成多线程流水线处理器的设计优化以及实现工作：首先对多线程流水线处理器的指令集以及五级流水线设计和结构进行了详细分析。多线程流水线处理器主要针对网络数据包的处理，相较于一般指令集，多线程流水线处理器指令集对其中一些指令进行了增减；针对多线程流水线处理器在设计时的流水线冲突问题，对于数据冲突和控制冲突分别进行了分析并给出了解决方案。其次，在完成基于SMIC0.13μm工艺的ASIC实现过程中，首先分析了从FPGA到ASIC设计的转换过程中遇到的问题及解决方案。其次，从综合约束、综合器优化，设计优化等方面论述了XDNP多线程流水线处理器及仲裁的综合和优化过程，重点说明了综合的时序违例和优化采取的方法。经过优化后的多线程流水线处理器最高工作频率达到300MHz，超过系统设计目标频率要求，并且完成了对多线程流水线处理器的综合后验证工作。最后根据综合得到的网表和约束文件参与完成了多线程流水线处理器的物理设计布局布线工作。
[Abstract]:The exponential growth of network users and data traffic requires wider bandwidth and faster processing speed. As a programmable ASIC processor, network processor can provide high performance processing speed similar to ASIC, and provide flexibility similar to general processor. Therefore, it meets the performance requirements of many applications. As the core design unit of network processor, the task of multithreading pipeline processor is to complete the verification of all packets through network processor, packet header processing and classification, table lookup and forwarding, and storage of packets in storage unit. Packet head modification, packet forwarding to the correct port, etc. Therefore, the performance of network processors is largely determined by the design of multithreaded pipelined processors. The frequency of multithreaded pipelined processors directly affects the working frequency, throughput and overall performance of the whole design platform. This paper mainly completes the design optimization and implementation of multithreaded pipeline processor. Firstly, the instruction set and five-stage pipeline design and structure of multithreaded pipeline processor are analyzed in detail. Multi-thread pipelined processor is mainly aimed at the processing of network data packet. Compared with general instruction set, multi-thread pipeline processor instruction set adds and subtracts some of the instructions. Aiming at the problem of pipeline conflict in the design of multithreaded pipelined processor, the data conflict and control conflict are analyzed and the solutions are given. Secondly, in the process of ASIC implementation based on SMIC0.13 渭 m process, the problems and solutions in the conversion process from FPGA to ASIC are analyzed. Secondly, the synthesis and optimization process of XDNP multithreaded pipeline processor and arbitration are discussed from the aspects of synthesis constraint, synthesizer optimization and design optimization. The optimized multithreaded pipelined processor has the highest working frequency of 300MHz, which exceeds the target frequency requirement of the system design, and the synthesis and verification of the multithreaded pipelined processor is completed. Finally, the physical layout and routing of multithreaded pipeline processor is completed according to the network table and constraint file.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332;TN47
本文编号：2353638
[Abstract]:The exponential growth of network users and data traffic requires wider bandwidth and faster processing speed. As a programmable ASIC processor, network processor can provide high performance processing speed similar to ASIC, and provide flexibility similar to general processor. Therefore, it meets the performance requirements of many applications. As the core design unit of network processor, the task of multithreading pipeline processor is to complete the verification of all packets through network processor, packet header processing and classification, table lookup and forwarding, and storage of packets in storage unit. Packet head modification, packet forwarding to the correct port, etc. Therefore, the performance of network processors is largely determined by the design of multithreaded pipelined processors. The frequency of multithreaded pipelined processors directly affects the working frequency, throughput and overall performance of the whole design platform. This paper mainly completes the design optimization and implementation of multithreaded pipeline processor. Firstly, the instruction set and five-stage pipeline design and structure of multithreaded pipeline processor are analyzed in detail. Multi-thread pipelined processor is mainly aimed at the processing of network data packet. Compared with general instruction set, multi-thread pipeline processor instruction set adds and subtracts some of the instructions. Aiming at the problem of pipeline conflict in the design of multithreaded pipelined processor, the data conflict and control conflict are analyzed and the solutions are given. Secondly, in the process of ASIC implementation based on SMIC0.13 渭 m process, the problems and solutions in the conversion process from FPGA to ASIC are analyzed. Secondly, the synthesis and optimization process of XDNP multithreaded pipeline processor and arbitration are discussed from the aspects of synthesis constraint, synthesizer optimization and design optimization. The optimized multithreaded pipelined processor has the highest working frequency of 300MHz, which exceeds the target frequency requirement of the system design, and the synthesis and verification of the multithreaded pipelined processor is completed. Finally, the physical layout and routing of multithreaded pipeline processor is completed according to the network table and constraint file.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332;TN47
【参考文献】
相关期刊论文 前1条
1 孟李林;;FPGA和ASIC设计特点及应用探讨[J];半导体技术;2006年07期
本文编号：2353638
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