70nm分离栅工艺快闪存储器擦写性能的改进
发布时间：2018-11-26 09:53
【摘要】：随着电子产品的普及,闪存作为当今主流的存储载体得到迅速地推广,其技术也得到迅猛地发展。分离栅快闪存储器,作为闪存的一种,由于具有高效的编程速度以及完全避免过擦除的能力,无论是在单体还是嵌入式产品方面都得到了人们更多的关注。目前,分离栅快闪存储器已被广泛地应用于个人电脑、数码器材、移动终端、智能卡等产品。 本文首先介绍了分离栅快闪存储器的工作原理及70nm分离栅工艺快闪存储器的实现方法。该分离栅结构的快闪存储器,采用源端沟道热电子注入(Source-Side Hot Electron injection)机制进行编程操作,采用浮栅和擦除栅两层多晶硅间电场增强型隧穿(Poly-to-Poly Enhance Tunneling)进行擦除操作,具有着良好的可靠性能和数据保持能力。 随着闪存市场高集成度的发展需求,分离栅快闪存储器的尺寸也在逐渐地缩小。在这一缩微过程中其面临着擦除效率低下和编程存在干扰的问题。在擦除过程中,由于在70nmm节点分离栅闪存中不再特意采用浮栅尖角(tip),没有足够的浮栅到擦除栅的正向隧穿电压,浮栅中部分电子容易被其和擦除栅间的隧穿氧化膜介质俘获,从而无法彻底擦除。在编程过程中,虽然其分离栅结构有高效的编程机制,但是未被编程的单元由于与正在被编程的单元共享位线或者字线,受所加电压的影响而被编程。原因是分离栅沟道带带隧穿效应产成的电子-空穴对,在浮栅氧化层发生隧穿并导致浮栅阈值电压减小,发生了编程干扰现象。本文通过大量实验,从结构和工艺优化方面探讨对于分离栅快闪存储器如何提高它的擦除效率(通过降低浮栅初始阈值电压,改变浮栅到擦除栅侧的结构形貌等)和降低它的编程干扰(整合优化存储单元离子注入工艺),进而改进了70nm分离栅工艺快闪存储器的擦写性能。 本论文的研究课题来源于企业的研发实践,因此对于同类型的闪存产品开发和生产制造具有一定的参考意义。
[Abstract]:With the popularity of electronic products flash memory as the mainstream storage carrier has been rapidly popularized and its technology has been rapidly developed. As a kind of flash memory, separation gate flash memory has attracted more and more attention in both single and embedded products due to its high programming speed and the ability to avoid over erasure completely. At present, the separation gate flash memory has been widely used in personal computers, digital devices, mobile terminals, smart cards and other products. This paper first introduces the working principle of the separating gate flash memory and the realization method of the 70nm separation gate technology flash memory. The flash memory with the separation gate structure is programmed by the source end channel hot electron injection (Source-Side Hot Electron injection) mechanism. The electric-field enhanced tunneling (Poly-to-Poly Enhance Tunneling) with floating gate and erasure gate has good reliability and data retention. With the development of high integration in flash memory market, the size of separating gate flash memory is gradually shrinking. In this process, it is faced with the problems of low erasure efficiency and programming interference. In the process of erasing, the forward tunneling voltage from floating gate to erasure gate is not enough because the floating gate angle (tip), is not specially used in the 70nmm node separation gate flash memory. Some electrons in the floating gate are easily captured by the tunneling oxide film medium between them and the erasure gate, so they can not be completely erased. In the process of programming, although the separated gate structure has an efficient programming mechanism, the unprogrammed units are programmed because they share bit lines or word lines with the units being programmed, and are affected by the applied voltage. The reason is that the electron-hole pair produced by the tunneling effect of the separated gate channel band leads to tunneling in the floating gate oxide layer which results in the decrease of the threshold voltage of the floating gate and the programming interference occurs. Through a large number of experiments, this paper discusses how to improve the erasure efficiency of the separation gate flash memory from the aspects of structure and process optimization (by reducing the initial threshold voltage of the floating gate. By changing the structure morphology of the floating gate to erasing the gate side and reducing its programming interference (integrating the optimized memory cell ion implantation process), the erasure performance of the flash memory in the 70nm separation gate process is improved. The research topic of this paper comes from the enterprise's R & D practice, so it has certain reference significance for the development and manufacture of the same type flash memory products.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333
本文编号：2358211
[Abstract]:With the popularity of electronic products flash memory as the mainstream storage carrier has been rapidly popularized and its technology has been rapidly developed. As a kind of flash memory, separation gate flash memory has attracted more and more attention in both single and embedded products due to its high programming speed and the ability to avoid over erasure completely. At present, the separation gate flash memory has been widely used in personal computers, digital devices, mobile terminals, smart cards and other products. This paper first introduces the working principle of the separating gate flash memory and the realization method of the 70nm separation gate technology flash memory. The flash memory with the separation gate structure is programmed by the source end channel hot electron injection (Source-Side Hot Electron injection) mechanism. The electric-field enhanced tunneling (Poly-to-Poly Enhance Tunneling) with floating gate and erasure gate has good reliability and data retention. With the development of high integration in flash memory market, the size of separating gate flash memory is gradually shrinking. In this process, it is faced with the problems of low erasure efficiency and programming interference. In the process of erasing, the forward tunneling voltage from floating gate to erasure gate is not enough because the floating gate angle (tip), is not specially used in the 70nmm node separation gate flash memory. Some electrons in the floating gate are easily captured by the tunneling oxide film medium between them and the erasure gate, so they can not be completely erased. In the process of programming, although the separated gate structure has an efficient programming mechanism, the unprogrammed units are programmed because they share bit lines or word lines with the units being programmed, and are affected by the applied voltage. The reason is that the electron-hole pair produced by the tunneling effect of the separated gate channel band leads to tunneling in the floating gate oxide layer which results in the decrease of the threshold voltage of the floating gate and the programming interference occurs. Through a large number of experiments, this paper discusses how to improve the erasure efficiency of the separation gate flash memory from the aspects of structure and process optimization (by reducing the initial threshold voltage of the floating gate. By changing the structure morphology of the floating gate to erasing the gate side and reducing its programming interference (integrating the optimized memory cell ion implantation process), the erasure performance of the flash memory in the 70nm separation gate process is improved. The research topic of this paper comes from the enterprise's R & D practice, so it has certain reference significance for the development and manufacture of the same type flash memory products.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333
【共引文献】
相关期刊论文 前2条
1 孟庆龙;张永;;单片机应用中几个问题的解决方法[J];信息技术与信息化;2010年03期
2 刘智朋;罗洪元;阳小珊;邱全伟;郑良;;闪存循环位图的损耗均衡机制研究[J];计算机工程与设计;2013年02期
，本文编号：2358211
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