高性价比DSP中指令Cache的研究与设计

发布时间：2018-11-26 11:18

【摘要】：系统吞吐量是处理器性能的重要衡量标准,而通常其往往受CPU的机能所限制。有研究表明快速存储器芯片和下一个最快的速度等级之间的价格差异可以高达50%或100%,然而存储器只能获得额外的20%的速度,不幸的是CPU的速度并不能得到相应的提升。所以为了开发一种高性价比的DSP处理器,Cache的设计则成了提高处理器系统性能的一个关键因素。Cache的研究已经成了当下DSP处理器开发中的一个热门话题。本文主要针对32位定点DSP处理器AXP32(AXP32的主频最高可达150 MHz,外设频率最高达40 MHz),而提出了“两级缓存”结构的设计。为了提高CPU向外部存储器取指的速度,便在CPU和外部存储器之间插入了一个指令Cache,此为“第一级缓存”。该指令Cache设计的容量为512 B,块大小为16 B,映像规则为直接映像,根据数字IC设计的基本流程,将指令Cache划分为两大模块:数据部分和控制部分。数据部分主要实现查找和比较的功能,而控制部分则根据查找结果实现指令Cache的下一步操作。“第二级缓存”的设计主要是基于外挂SPI FLASH,为了提升DSP内核与外部FLASH之间的通信速度,在SPI外设与DSP内核通信之间插入了一个异步FIFO。该异步FIFO使用格雷码计数来同步读写指针,并对读写地址产生逻辑、空满标志判断逻辑进行了详细的电路设计和说明。在本课题的设计中,使用Verilog编程语言对本课题的设计进行RTL级实现,并通过Cadence的NC-Verilog仿真工具对指令Cache和异步FIFO进行功能仿真,仿真通过之后便使用Synopsys的Design Compiler综合工具来优化代码的设计。综合结果如下:指令Cache的总面积为0.351 mm2,功耗为38.85 mW,时钟频率最高可达150 MHz;异步FIFO的总面积为0.011 mm2,功耗为452.95μW,读时钟频率最高可达100 MHz。
[Abstract]:System throughput is an important measure of processor performance, which is often limited by the capabilities of CPU. Studies have shown that the price difference between the fast memory chip and the next fastest speed level can be as high as 50% or 100%, but the memory can only get an additional 20% speed. Unfortunately, the speed of the CPU cannot be increased accordingly. So in order to develop a kind of DSP processor with high performance-price ratio, the design of Cache has become a key factor to improve the performance of processor system. The research of Cache has become a hot topic in the development of DSP processor. In this paper, the design of "two-stage buffer" architecture is presented for 32-bit fixed-point DSP processor AXP32 (the main frequency of AXP32 can be up to 150 MHz, peripheral frequency up to 40 MHz),). In order to improve the speed of CPU to refer to external memory, an instruction Cache, is inserted between CPU and external memory, which is called "first stage cache". The design capacity of the instruction Cache is 512B, the block size is 16B, and the image rule is the direct image. According to the basic flow of digital IC design, the instruction Cache is divided into two modules: data part and control part. The data part mainly realizes the function of searching and comparing, while the control part realizes the next operation of instruction Cache according to the lookup result. The design of the "second level cache" is mainly based on the external SPI FLASH,. In order to speed up the communication between the DSP kernel and the external FLASH, an asynchronous FIFO. is inserted between the SPI peripheral and the DSP kernel. The asynchronous FIFO uses Graycode count to synchronize the read / write pointer, and gives a detailed circuit design and description for the logic of the read-write address and the judgment logic of the empty full flag. In the design of this subject, we use Verilog programming language to realize the design of this subject at RTL level, and use the NC-Verilog simulation tool of Cadence to simulate the function of instruction Cache and asynchronous FIFO. After the simulation is passed, Synopsys's Design Compiler synthesis tool is used to optimize the code design. The results are as follows: the total area of instruction Cache is 0.351 mm2, the power consumption is 38.85 mW, the maximum clock frequency is 150 MHz; asynchronous FIFO, the total area is 0.011 mm2, the power consumption is 452.95 渭 W, and the read clock frequency is up to 100 MHz..
【学位授予单位】：湘潭大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332

【参考文献】