基于FPGA的高速实时数据采集存储系统的设计
发布时间：2018-11-28 07:49
【摘要】：随着现代科技高速发展,在工业生产和科学研究上如无线通信、图像处理、核磁共振波谱仪等领域,都需要在各级设备间高速传输大量的数据。因此需要在系统设计中运用大容量、高速的存储介质。随着科技进的步,人们开始使用内存,内存产品也正在不断演进,从最初的DRAM一直发展到今天在本论文中使用到的DDR3SDRAM。在时序控制方面,FPGA芯片具有较高的时钟频率和丰富的硬件资源,能够快速有效的控制复杂的组合逻辑和时序逻辑电路。所以通过将FPGA和DDR3SDRAM相结合的接口时序设计,可以在大容量与高速率的采集存储系统中起到核心控制作用。 基于该背景,在深入阅读和理解了FPGA开发流程和DDR3SDRAM的控制原理、存储结构、接口时序等知识后,本文提出了基于Xilinx公司的Spartan6FPGA作为控制核心,Micron公司的DDR3SDRAM作为存储介质,并通过USB2.0系统进行数据传输的高速采集与存储系统,以满足现代工业与科学研究中高速、高实时性的数据采集存储要求。 本论文首先介绍了高速采集存储系统的技术背景和国内外发展状况,并针对现有使用DDR或者DDR2内存的该系统,提出使用DDR3内存能更快速读写数据并具有更大存储容量的方案。其次,给出了搭建本系统的总体架构和论文设计的思路,即如何实现基于FPGA控制的DDR3控制器,并确立了控制器系统中各个模块的组成。然后通过ISE12.4开发平台和Verilog HDL的设计输入方式,并结合了开放的IP核资源,对每个模块进行了详细的逻辑分析与设计。最后运用硬件环境对所设计的系统进行测试,分析了系统资源耗用情况,系统实时性和使用chipscope逻辑分析仪工具对该系统进行了功能验证。 验证结果说明,基于FPGA与DDR3的高速采集存储系统,数据吞吐量与读写速率较现有系统有很大的提升,达到了最初系统设计的要求。在长时间不断电工作下稳定运行,没有误码的产生。
[Abstract]:With the rapid development of modern science and technology, in industrial production and scientific research, such as wireless communication, image processing, nuclear magnetic resonance spectrometer and other fields, it is necessary to transfer a large amount of data at high speed between various devices. Therefore, it is necessary to use large capacity and high speed storage media in the system design. With the advance of technology, people begin to use memory, and memory products are evolving, from the beginning of DRAM to the DDR3SDRAM. used in this paper. In the aspect of timing control, FPGA chip has high clock frequency and abundant hardware resources, and can control complex combinatorial logic and sequential logic circuits quickly and effectively. Therefore, by combining FPGA and DDR3SDRAM interface timing design, it can play a central control role in large capacity and high speed acquisition and storage system. Based on this background, after deeply reading and understanding the FPGA development process and the knowledge of DDR3SDRAM control principle, storage structure, interface timing and so on, this paper proposes Spartan6FPGA based on Xilinx as the control core and DDR3SDRAM of Micron as the storage medium. In order to meet the requirement of high-speed and real-time data acquisition and storage in modern industrial and scientific research, a high-speed data acquisition and storage system is implemented through USB2.0 system. This paper first introduces the technical background of high-speed acquisition and storage system and the development situation at home and abroad. Aiming at the existing system which uses DDR or DDR2 memory, this paper puts forward a scheme of using DDR3 memory to read and write data more quickly and have more storage capacity. Secondly, the overall architecture of the system and the design idea of the paper are given, that is, how to realize the DDR3 controller based on FPGA control, and the composition of each module in the controller system is established. Then through the ISE12.4 development platform and Verilog HDL design input mode, and combined with the open IP core resources, each module is analyzed and designed in detail. Finally, the system is tested by hardware environment, the system resource consumption is analyzed, the real-time performance of the system is analyzed, and the function of the system is verified by using the chipscope logic analyzer tool. The verification results show that the data throughput and read / write rate of the high speed acquisition and storage system based on FPGA and DDR3 are greatly improved than the existing system, and meet the requirements of the original system design. In a long time without power off under the stable operation, there is no error code generation.
【学位授予单位】：武汉理工大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP274.2;TP333
本文编号：2362263
[Abstract]:With the rapid development of modern science and technology, in industrial production and scientific research, such as wireless communication, image processing, nuclear magnetic resonance spectrometer and other fields, it is necessary to transfer a large amount of data at high speed between various devices. Therefore, it is necessary to use large capacity and high speed storage media in the system design. With the advance of technology, people begin to use memory, and memory products are evolving, from the beginning of DRAM to the DDR3SDRAM. used in this paper. In the aspect of timing control, FPGA chip has high clock frequency and abundant hardware resources, and can control complex combinatorial logic and sequential logic circuits quickly and effectively. Therefore, by combining FPGA and DDR3SDRAM interface timing design, it can play a central control role in large capacity and high speed acquisition and storage system. Based on this background, after deeply reading and understanding the FPGA development process and the knowledge of DDR3SDRAM control principle, storage structure, interface timing and so on, this paper proposes Spartan6FPGA based on Xilinx as the control core and DDR3SDRAM of Micron as the storage medium. In order to meet the requirement of high-speed and real-time data acquisition and storage in modern industrial and scientific research, a high-speed data acquisition and storage system is implemented through USB2.0 system. This paper first introduces the technical background of high-speed acquisition and storage system and the development situation at home and abroad. Aiming at the existing system which uses DDR or DDR2 memory, this paper puts forward a scheme of using DDR3 memory to read and write data more quickly and have more storage capacity. Secondly, the overall architecture of the system and the design idea of the paper are given, that is, how to realize the DDR3 controller based on FPGA control, and the composition of each module in the controller system is established. Then through the ISE12.4 development platform and Verilog HDL design input mode, and combined with the open IP core resources, each module is analyzed and designed in detail. Finally, the system is tested by hardware environment, the system resource consumption is analyzed, the real-time performance of the system is analyzed, and the function of the system is verified by using the chipscope logic analyzer tool. The verification results show that the data throughput and read / write rate of the high speed acquisition and storage system based on FPGA and DDR3 are greatly improved than the existing system, and meet the requirements of the original system design. In a long time without power off under the stable operation, there is no error code generation.
【学位授予单位】：武汉理工大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP274.2;TP333
【引证文献】
相关硕士学位论文 前2条
1 刘立;基于MPSoC的DDR3存储器接口设计[D];南京大学;2013年
2 郭浩;基于FPGA的运动目标检测系统的设计与实现[D];武汉理工大学;2013年
，本文编号：2362263
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